Browsing by Author "Lee, JW"

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A study of the threshold voltage variations for ultrathin body double gate SOI MOSFETs
(2004)
Tang, CS
;
Lo, SC
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Lee, JW
;
Tsai, JH
;
Li, YM
Silicon on insulator (SOI) devices have been of great interest in these years. In this paper, simulation with density-gradient transport model is performed to examine the variation of threshold voltage (VTH) for double gate SOI MOSFETs. Different thickness of silicon (Si) film, oxide thickness, channel length and doping concentration are considered in this work. According to the numerical study, both drift-difftision (DD) and density gradient (DG) models demonstrate that the thickness of Si film greatly affects the threshold voltage (5 similar to 15% variation). It is found that the thickness of Si film decreases, VTH variation increases; and the dependence relation is nonlinear. Therefore, this effect must be taken into account for the realization of double gate SOI ULSI circuit.
A three-dimensional simulation of electrostatic characteristics for carbon nanotube array field effect transistors
(2005-08-01)
Li, YM
;
Chou, HM
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Lee, JW
;
Lee, BS
;
電子物理學系
We, in this paper, study the electrostatic characteristics and the gate capacitances for carbon nanotube (CNT) array field effect transistors (FETs). The explored CNT-array FET is with three configurations of gate electrode, the top gate, the wrap around gate, and the bottom gate. Taking the pitch distance of structures and the gate length of CNT FET into consideration, a three-dimensional (3D) electrostatic simulation are performed by using an adaptive finite volume method, where different gate capacitance are calculated and compared. It is found that there is at least a 20% difference in calculating the gate capacitance between the 2D and 3D modeling and simulations. Our 3D simulation shows that a wrap around gate gives the largest gate capacitance among structures. A bottom gate possesses the weakest gate controllability. Effects of the pitch distance and the gate length on the gate capacitances of CNT-array FET are investigated. Results of the 3D electrostatic simulations can be applied to estimate the magnitude of the on-current of CNT FETs. (c) 2005 Elsevier B.V. All rights reserved.
Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era.
(2006-05-01)
Lee, JW
;
Li, YM
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電信工程研究所
;
友訊交大聯合研發中心
;
Institute of Communications Engineering
In this paper, the floating charge effect is considered in the design of new fully silicided NMOSFETs for designing electrostatic discharge (ESD) protection circuit consisting of nanodevices. According to the designed, fabricated, and studied new fully silicided ESD protection nanodevices (e.g., 90-nm CMOS devices), our investigation demonstrates that there is a significant improvement in sustaining ESD robustness than that of the conventional fully silicided device. Furthermore, it has an excellent electrical efficiency compared with that of drain-ballast resistor-tied devices. Moreover, our novel design exhibits a higher driving current and better reliability without suffering the off-state current of the fully silicided devices. Those good characteristics are especially suitable for the output buffer design in which both driving capability and ESD robustness have to be considered.
Electrostatic discharge protection under pad design for copper-low-K VLSI circuits
(2004-04-01)
Lee, JW
;
Li, YM
;
Chao, A
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Tang, H
;
友訊交大聯合研發中心
An electrostatic discharge (ESD) under pad structure is proposed and demonstrated for the novel copper-low-K circuit design. By using this approach, the density of both devices and pads could be markedly improved; in a rough estimation, approximately five to twenty percent of the chip area could be saved. Moreover, tests of ESD, latch-up, and bond yield are performed and are found to be better than those of the conventional ones. The designed structure could be considered as a very effective achievement, and this is particularly true for the sub-0.1 mu m circuit with copper-low-K interconnections.
Growing high-performance tunneling oxide by CF4 plasma pretreatment
(2003-01-01)
Chang, TY
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Lee, JW
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Lei, TF
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Lee, CL
;
Wen, HC
Thin tunneling oxides grown on a CF4 pretreated silicon substrate were prepared and investigated for the first time. The tunneling current of the CF4-treated oxide is about three orders of magnitude higher than that of thermal oxide; furthermore, the stress-induced anomalous current and low electric field leakage current were greatly suppressed. The improvement was attributed to the incorporation of fluorine in the oxide region. Both control and CF4-treated devices exhibited comparable channel mobility. However, pretreatment with CF4 markedly improved the reliability of the insulator. This oxide is highly promising for fabricating low-voltage electrically erasable and programmable read-only memories (EEPROMs) without increasing the complexity of the process. (C) 2002 The Electrochemical Society.
High reliability polyoxide fabricated by using TEOS oxide deposited on disilane polysilicon film
(2001-04-01)
Lee, JW
;
Lee, CL
;
Lei, TF
;
Lai, CS
;
電子工程學系及電子研究所
This paper reports the TEOS oxide deposited on the polysilicon film which was prepared by using the disilane chemical vapor deposition. Compared to the thermally grown oxide or TEOS (tetra-ethyl-ortho-silicate) oxide deposited on the conventional silane polysilicon him, it had symmetrical J-E characteristics that had lower leakage currents but much higher breakdown field, a lower electron trapping rate, and a much larger charge to breakdown. These good properties are attributed to the smoother surface of the deposited disilane poly-I film and the more incorporation of nitrogen during the rapid thermal annealing (RTA) in N2O ambient. It is suitable to be as the inter-polyoxide of the electrically-erasable programmable read only memory (EEPROM).
High reliability ultrathin interpolyoxynitride dielectrics prepared by N2O plasma annealing
(2003-12-01)
Wang, JC
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Lee, JW
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Kuo, LT
;
Lei, TF
;
Lee, CL
This work addresses the preparation of ultrathin (effective oxide thickness, 42 Angstrom) interpoly-oxynitride (SiOxNy) films by annealing thin nitride films with high density N2O plasma and N2O rapid thermal annealing. The proposed oxynitride dielectrics formed using N2O plasma annealing exhibited low gate leakage current, high breakdown electric field, long ten-year lifetime, and large effective barrier height. These superior properties can be attributed to the high concentration of oxygen incorporated in the poly-II/nitride interface and a reduction of the trap density of the interpoly-oxynitride films. The dielectric is a suitable substitute for the inter-polyoxide of electrically-erasable programmable read only memory. (C) 2003 The Electrochemical Society.
Highly reliable nickel silicide formation with a Zr capping layer
(2003-05-01)
Lee, TL
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Lee, JW
;
Lee, MC
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Lei, TF
;
Lee, CL
Zr is proposed to be the capping layer for nickel silicide to obtain a stable low resistance contact system even at an annealing temperature as high as 850degreesC. A NiSi monolayer is the only phase observed in those samples annealed from 500 to 850degreesC. Experimental results from transmission electron microscopy and X-ray diffractometry analysis show that the agglomeration and precipitate of nickel silicide problems which are usually encountered in the NiSi system are eliminated. (C) 2003 The Electrochemical Society.
Improvements in both thermal stability of Ni-silicide and electrical reliability of gate oxides using a stacked polysilicon gate structure
(2001-09-01)
Lee, JW
;
Lin, SX
;
Lei, TF
;
Lee, CL
;
電子工程學系及電子研究所
A process design is presented for improving the thermal stability of Ni-silicide (nickel-silicide) using a stacked polysilicon gate structure. The Ni-silicide formed has low sheet resistance up to 800 degreesC on a silicidation process. Additionally, the metal-oxide-semiconductor (MOS) capacitors fabricated using these proposed gate structures demonstrate higher electrical reliability for gate oxides than those of nonstacked films. That is, the gate oxides of the MOS capacitors were only slightly degraded after silicidation step at 800 degreesC. In conclusion, the Ni-silicide formed on those stacked polysilicon gates are attractive in fabricating ultralarge scale integration (ULSI) circuits because both the thermal stability of Ni-silicide and the reliability of gate oxides are improved simultaneously. (C) 2001 The Electrochemical Society.
Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs
(2005-09-01)
Li, YM
;
Chou, HM
;
Lee, JW
;
電信工程研究所
;
友訊交大聯合研發中心
In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowing, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire Fin FETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.
Numerical simulation of quantum effects in high-k gate dielectric MOS structures using quantum mechanical models
(2002-08-01)
Li, YM
;
Lee, JW
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Tang, TW
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Chao, TS
;
Lei, TF
In this paper the electrical characteristics of metal oxide semiconductor (MOS) capacitors with high-k gate dielectric are investigated with quantum mechanical models. Both the self-consistent Schrodinger-Poisson (SP) model and the density gradient (DG) model are solved simultaneously to study quantum confinement effects (QCEs) for MOS capacitors. A computationally efficient parallel eigenvalue solution algorithm and a robust monotone iterative (MI) finite volume (FV) scheme for the SP and DG models are systematically proposed and successfully implemented on a Linux cluster, respectively. With the developed simulator, we can extract the effective gate oxide thickness from capacitance voltage (C-V) measurements for TaN and Al gate NMOS capacitors with ZrO2 and SiO2 gate dielectric materials. We found that quantization effects of 5.0 nut Z(r)O(2) MOS samples cannot be directly equivalent to commonly quoted effects of 1.5 nm SiO2 MOS samples. Achieved benchmarks are also included to demonstrate excellent performances of the proposed computational techniques. (C) 2002 Elsevier Science B.V. All rights reserved.
Optimization of the anti-punch-through implant for electrostatic discharge protection circuit design
(2003-04-01)
Li, YM
;
Lee, JW
;
Sze, SM
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電子工程學系及電子研究所
;
友訊交大聯合研發中心
In this study, an optimal anti-punch-through implant for electrostatic discharge (ESD) protection devices is investigated. By solving a two-dimensional (2D) hydrodynamic (HD) device model as well as a lattice temperature equation numerically, the current density, carrier temperature, and parasitic capacitance of four different device structures are analyzed and compared for suppressing short-channel effects, reducing device heating, and improving ESD robustness simultaneously. The structure difference among these four devices is the location of anti-punch-through implantation; that is: (a) the Type 1 device is the control device without anti-punch-through implantation; (b) the Type 2 device is the device with anti-punch-through implantation under the source/drain extension; (c) the Type 3 device, with anti-punch-through implantation under the deep source/drain junction; and (d) the Type 4 device, with anti-punch-through implantation surrounding all junctions. By comparing these four device structures, we find that the Type 4 device not only has a lower electron temperature (and hence good thermal immunity) but also has a larger current density under an applied high bias. Therefore, this device maintains a higher driving capacity without producing a higher amount of heat and is suitable for the ESD protection device application.
Performance and reliability of poly-Si TFTs on FSG buffer layer
(2005-07-01)
De Wang, S
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Chang, TY
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Chien, CH
;
Lo, WH
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Sang, JY
A novel and process-compatible scheme for fabricating poly-Si thin-film transistors (TFTs) on an FSG buffer layer was proposed and demonstrated. Experimental results reveal that remarkably improved device performance and uniformity can be achieved with appropriate fluorine concentration. The poly-Si TFTs fabricated on FSG layers have a higher on-current, a lower leakage current, and a higher field-effect mobility compared with the conventional poly-Si TFTs. Furthermore, the incorporation of fluorine also increased the reliability of poly-Si TFTs against hot carrier stressing, which is attributed to the formation of Si-F bonds.
Phase transformations in an Fe-8Al-10Ni-2C alloy
(2001-02-02)
Lee, JW
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Liu, TF
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材料科學與工程學系
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Department of Materials Science and Engineering
Phase transformations in an Fe-8Al-30Mn-1.5Si-1.5C alloy
(2001-03-01)
Lee, JW
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Liu, TF
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材料科學與工程學系
;
Department of Materials Science and Engineering
The phase transformations in an Fe-8Al-30Mn-1.5Si-1.5C alloy has been investigated by means of transmission electron microscopy. In the as-quenched condition, the microstructure of the alloy was austenite phase containing fine (Fe,Mn)(3)AlC carbides. The fine (Fe,Mn)(3) AlC carbides were formed during quenching by a spinodal decomposition. When the as-quenched alloy was aged at temperatures ranging from 550 to 1000 degreesC, the phase transformation sequence as the aging temperature increased was found to be (Fe,Mn)(3)AlC carbide + D0(3) --> (Fe, Mn)(3)AlC carbide + B2 --> (Fe, Mn)(3)AlC carbide + alpha --> gamma. This transformation has never before been observed in the Fe-Al-Mn-C and Fe-Al-Mn-Si-C alloys. (C) 2001 Elsevier Science B.V. All rights reserved.
Quantum mechanical corrected simulation program with integrated circuit emphasis model for simulation of ultrathin oxide metal-oxide-semiconductor field effect transistor gate tunneling current
(2005-04-01)
Li, YM
;
Yu, SM
;
Lee, JW
;
友訊交大聯合研發中心
;
D Link NCTU Joint Res Ctr
In this paper we present a quantum mechanical corrected gate tunneling current model for simulating ultrathin oxide metal-oxide-semiconductor (MOS) devices. By approximating the physically based Esaki-Tsu tunneling formula and explicitly modeling the classical (CL) and quantum mechanical (QM) corrected surface potential, this model successfully predicts the gate tunneling current for ultrathin oxide MOS samples under different applied biases. Simply assuming all tunneling electrons have the same kinetic energy, the Esaki-Tsu tunneling formula is first simplified so that it can be solved without encountering numerical integral. problems. Numerical solutions of the classical Poisson equation and Schrodinger-Poisson equations are then used to analytically express the CL and QM corrected surface potentials explicitly in terms of substrate doping, thickness of the gate oxide (T(ox)(ox)(), and applied bias. The full explicit, physical-based, and QM corrected gate tunneling current model quantitatively shows good agreement with the technology computer-aided design (TCAD) simulation. Compared with the measured gate tunneling current from fabricated 0.12 mm n-type Metal-Oxide-Semiconductor Field Effect Transistors (NMOSFETs) with three different thicknesses of gate oxide, T) = 1, 1.2 and 1.5 nm, the QM corrected gate tunneling current model shows good accuracy for various ultrathin oxide samples under different biases. However, the gate tunneling current model with the CL surface potential results in one order of magnitude underestimation in comparison with the measured data. We implement the gate tunneling current model into the simulation program with integrated circuit emphasis (SPICE) simulator and perform a DC simulation. Simulated results preliminarily show the effect of the gate leakage current on the drain current without any numerical convergence problem.
Simulation of electrical characteristics of surrounding- and omega-shaped-gate nanowire FinFETs
(2004)
Tang, CS
;
Yu, SM
;
Chou, HM
;
Lee, JW
;
Li, YM
In this paper, electrical characteristics of sub-10 not nanowire FinFETs are investigated using a three-dimensional (3D) quantum correction simulation. Two different nanowire FinFETs, surrounding-gate FinFET and omega-shaped-gate one, are simulated with density-gradient-based model and compared in terms of on/off current, turn-on resistance, gate capacitance. It is found that the characteristic difference between surrounding-gate FinFET and omega-shaped-gate FinFET with a 70% coverage is insignificant. However, the former possesses better DIBL effect than that latter with different coverage ratios. Our examination presented here is useful in the fabrication of omega-shaped nanowire FinFETs.
The enhancement of nitrogen incorporation in RTN2O annealed TEOS oxide fabricated on disilane-based polysilicon films
(2001-08-01)
Lee, JW
;
Chen, WD
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Lei, TF
;
Lee, CL
;
電子工程學系及電子研究所
Disilane-based stacked structures were first proposed to demonstrate that the nitrogen incorporation was enhanced in the RTN2O annealed tetraethylorthosilicate (TEOS) oxide fabricated on disilane-based polysilicon films. Compared with the oxide fabricated on the silane-based polysilicon film, the nitrogen incorporation in the disilane-based oxides is six times higher. To study the nitrogen incorporation effects on the RTN2O annealed TEOS oxides, the disilane-based polysilicon stacked on the silane-based polysilicon film structure was proposed. We found that the oxide quality was largely improved by the same surface morphology of bottom polysilicon films. We think the this approach could be used in fabricating dynamic random access memory (DRAM) to have better data retention characteristics and to improve the reliability of DRAM and flash memory devices. (C) 2001 The Electrochemical Society. [DOI: 10.1149/1.1383554] All rights reserved.
The influence of Cr alloying on microstructures of Fe-Al-Mn-Cr alloys
(2004-06-01)
Lee, JW
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Wu, CC
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Liu, TF
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材料科學與工程學系
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Department of Materials Science and Engineering
The effects of increasing chromium content on the phase transformations in Fe-Al-Mn-Cr alloys have been investigated by means of transmission electron microscopy and energy-dispersive X-ray spectrometry. The experimental results revealed that increasing the chromium addition would expand both the A12alpha-Mn and DO3 phase-field regions. (C) 2004 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved.
Thin oxides grown on disilane-based polysilicon
(2002-06-01)
Lee, JW
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Lei, TF
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Lee, CL
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This report describes the thin oxide (<10 nm) thermally grown on polysilicon film, which was prepared by disilane (Si2H6) chemical vapor deposition. In comparison with the thin oxide grown on conventional silane (SiH4) polysilicon film, the prepared oxides have lower leakage current,;. a lower electron trapping rate and a larger charge to breakdown distribution. These good properties are attributed to the smooth surface of the disilane poly-I film. This film is suitable for use as the interpoly oxide of electrically-erasable programmable read only memory.