Browsing by Author "Lee, Ko-Hui"

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A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer
(2013-03-01)
Lee, Ko-Hui
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Hf-based charge-trapping (CT) layers, including HfO2 and HfAlO, were employed in the fabrication of a CT-type memory with gate-all-around (GAA) poly-Si nanowire channels. It is shown that the GAA configuration can greatly enhance the programming/erasing efficiency as compared with the conventional planar scheme. It is also shown that the incorporation of Al into the dielectric can further improve the retention and endurance characteristics over the counterparts with a HfO2 trapping layer. Retardation of the recrystallization of the dielectric film with Al incorporation is postulated to be responsible for these observations.
Characteristics of poly-Si nanowire transistors with multiple-gate configurations
(2008)
Hsu, Hsing-Hui
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Lin, Homg-Chih
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Lee, Ko-Hui
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Huang, Jian-Fu
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Huang, Tiao-Yuan
Fabrication of High-Performance Poly-Si Thin-Film Transistors With Sub-Lithographic Channel Dimensions
(2014-11-01)
Lee, Ko-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A method for fabrication of tri-gate polycrystalline silicon (poly-Si) transistors with short channel length and width is proposed and demonstrated without employing costly lithographic tools. Specifically, the method employs a spacer formation technique to extend source and drain regions so as to scale down the channel length below sub-lithographic dimension. Concurrently, the channel width is scaled down below sub-lithographic dimension by using a photoresist (PR) trimming technique. Our results show that the reduction in the planar channel width is essential for suppressing the short-channel effects. Finally, devices with channel length of 120 nm and planar channel width of 110 nm are demonstrated with superior electrical characteristics in terms of small subthreshold swing (146 mV/dec) and low drain-induced-barrier-lowing value (100 mV/V).
Fabrication of tri-gated junctionless poly-Si transistors with I-line based lithography
(2014-04-01)
Lin, Cheng-I
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Lee, Ko-Hui
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電機工程學系
In this work, we have successfully demonstrated the feasibility of a method, which relies solely on I-line-based lithography, for fabricating sub-100nm tri-gated junctionless (JL) poly-Si nanowire (NW) transistors. This method employs sidewall spacer etching and photoresist (PR) trimming techniques to shrink the channel length and width, respectively. With this approach, channel length and width down to 90 and 93nm, respectively, are achieved in this work. The fabricated devices exhibit superior device characteristics with low subthreshold swing of 285mV/dec and on/off current ratio larger than 10(7). (C) 2014 The Japan Society of Applied Physics
Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels
(2014-04-01)
Tsai, Jung-Ruey
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Lee, Ko-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
A novel gate-all-around (GAA) poly-Si floating-gate (FG) memory device with triangular nanowire (NW) channels was fabricated and characterized in this work. The enhanced electric field around the corners of the NW channels boosts more electrons tunneling through the tunnel oxide layer during programming and erasing (P/E) processes, and thus the operation voltage markedly decreases. Furthermore, the nonlocalized trapping feature characteristic of the FG makes the injection of electrons easier during the programming operation, which was demonstrated by technology computer-aided design (TCAD) simulations. (C) 2014 The Japan Society of Applied Physics
Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices
(2011-07-01)
Luo, Cheng-Wei
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Lin, Horng-Chih
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Lee, Ko-Hui
;
Chen, Wei-Chen
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Hsu, Hsing-Hui
Trap-layer-engineered poly-Si nanowire silicon-oxide-nitride-oxide-silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxide/nitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer.
Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire
(2013-10-07)
Lee, Ko-Hui
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Tsai, Jung-Ruey
;
Chang, Ruey-Dar
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Lin, Horng-Chih
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Huang, Tiao-Yuan
A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings. (C) 2013 AIP Publishing LLC.
Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer
(2014-01-01)
Lee, Ko-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Gate-all-around (GAA) nanowire (NW) memory devices with a SiN- or Hf-based charge-trapping (CT) layer of the same thickness were studied in this work. The GAA NW devices were fabricated with planar thin-film transistors (TFTs) on the same substrate using a novel scheme without resorting to the use of advanced lithographic tools. Owing to their higher dielectric constant, the GAA NW devices with a HfO2 or HfAlO CT layer show greatly enhanced programming/erasing (P/E) efficiency as compared with those with a SiN CT layer. Furthermore, the incorporation of Al into the Hf-based dielectric increases the thermal stability of the CT layer, improving retention and endurance characteristics. (C) 2014 The Japan Society of Applied Physics
Novel Method for Fabrication of Tri-Gated Poly-Si Nanowire Field-Effect Transistors With Sublithographic Channel Dimensions
(2013-06-01)
Lee, Ko-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high-performance short-channel tri-gated polycrystalline-silicon nanowire (NW) field-effect transistor is developed by using simple sidewall spacer and lateral etching techniques without employing costly lithographic tools. Channel length of 120 nm and NW thickness of 25 nm can be easily formed by the self-aligned process. The device exhibits superior electrical characteristics because of the strong gate controllability: a subthreshold swing of 102 mV/dec, drain induced barrier lowing of 74.4 mV/V, and extremely high I-ON/I-OFF ratio of 4.4 x 10(8)(V-d = 1 V) are obtained.
Performance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-k Capping Layer
(2009-02-01)
Lee, Ko-Hui
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Hsu, Hsing-Hui
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control. (C) 2009 The Japan Society of Applied Physics