Browsing by Author "Lee, Shih-Wei"

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A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
(2015-02-01)
Chang, Chih-Wei
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Chou, Lei-Chun
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Huang, Po-Tsang
;
Wu, Shang-Lin
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Lee, Shih-Wei
We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 mu m CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5x5 mm(2) in area, with 16 channels of 150 mu m-in-length neural probe array on the back-side, 200 mu m-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5x6 probe array, 3x14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 mu W power consumption, 108 dB CMRR and 2.56 mu Vrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.
A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration
(2018-02-01)
Lee, Shih-Wei
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Kuo, Shu-Chiao
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.
A Novel Sealing Redistribution Layer Approach for Through-Glass via Fabrication
(2017-03-01)
Lee, Shih-Wei
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Chang, Geng-Ming
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Chang, Ching-Yun
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Chen, Kuan-Neng
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電子工程學系及電子研究所
A sealing redistribution layer (RDL) approach for the interposer fabrication is developed to simplify the conventional bottom-up process flow. By using this approach, bottom-up plating can achieve the integration of Cu-filler plating and its bottom RDL simultaneously. In this paper, through-glass via in glass interposer or 3-D integration is fabricated using the proposed approach. The electrical measurement and reliability tests indicate that the proposed approach can be an attractive candidate for interposer fabrication with great performance.
A TSV-Based Bio-Signal Package With mu-Probe Array
(2014-02-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Huang, Po-Tsang
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Chang, Chih-Wei
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Chiang, Cheng-Hao
Bio-signal probes providing stable observation with high quality signals are crucial for understanding how the brain works and how the neural signal transmits. Due to the weak and noisy characteristics of bio-signals, the connected interconnect length between the sensor and CMOS has significant impact on the bio-signal quality. In addition, long interconnections with wire bonding technique introduce noises and lead to bulky packaged systems. This letter presents an implantable through-silicon via (TSV) technology to connect sensors and CMOS devices located on the opposite sides of the chip for brain neural sensing applications. With the elimination of traditional wire bonding and packaging technologies, the quality of bio-signal can be greatly improved.
A TSV-Based Heterogeneous Integrated Neural-Signal Recording Device with Microprobe Array
(2014-01-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Cheng, Chuan-An
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Huang, Po-Tsang
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Chang, Chih-Wei
Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization. This paper presents a TSV-based heterogeneous integrated neural-signal recording device with microprobe array. By TSV, microprobe array and CMOS circuit make connection on the opposite sides of the chip. By measurement results on electrical characteristics of devices and TSV, this recording device is ready for bio-medical applications.
Advanced Crystal Component Package with Silicon TSV Interposer Using 3D Integration and Novel SU-8 Polymer Sealing Bonding Structure
(2014)
Shih, Jian-Yu
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Chen, Yen-Chi
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Lee, Shih-Wei
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Hu, Yu-Chen
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Chiu, Chih-Hung
In this paper, a novel crystal component package based on silicon TSV interposer substrate is demonstrated by using 3D integration technologies. It is distinct from conventional crystal component using ceramic-based substrate. This crystal component with advanced silicon-based substrate shows great manufacturability to replace traditional fabrication approach. In addition, the SU-8 sealing bonding structure provides the possibility to substitute for the conventional metal lid with reliability investigation. Finally, a novel silicon-based crystal component package with 3D integration is successfully fabricated through general semiconductor techniques to replace traditional manufacture.
Complementary inverter circuits based on p-SnO(2) and n-In(2)O(3) thin film transistors
(2008-06-09)
Dhananjay
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Chu, Chih-Wei
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Ou, Chun-Wei
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Wu, Meng-Chyi
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Ho, Zhong-Yo
Thin film transistors (TFTs) of indium oxide (In(2)O(3)) and tin oxide (SnO(2)) were fabricated on SiO(2) gate dielectric using reactive evaporation process. Structural investigation of the films revealed that In(2)O(3) films were polycrystalline in nature with preferred (222) orientation and SnO(2) films exhibited amorphous nature. The x-ray photoelectric spectroscopy measurements suggest that SnO(2) films were oxygen rich and presume mixed oxidation states of Sn, namely Sn(2+) and Sn(4+). While the In(2)O(3) based TFTs possess n-type channel conduction, SnO(2) based TFTs exhibited anomalous p-type conductivity. Integration of these n- and p-type devices resulted in complementary inverter with a gain of 11. (C) 2008 American Institute of Physics.
Complementary inverter circuits based on p-SnO2 and n-In2O3 thin film transistors
(2008-06-09)
Dhananjay
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Chu, Chih-Wei
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Ou, Chun-Wei
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Wu, Meng-Chyi
;
Ho, Zhong-Yo
Thin film transistors (TFTs) of indium oxide (In2O3) and tin oxide (SnO2) were fabricated on SiO2 gate dielectric using reactive evaporation process. Structural investigation of the films revealed that In2O3 films were polycrystalline in nature with preferred (222) orientation and SnO2 films exhibited amorphous nature. The x-ray photoelectric spectroscopy measurements suggest that SnO2 films were oxygen rich and presume mixed oxidation states of Sn, namely Sn2+ and Sn4+. While the In2O3 based TFTs possess n-type channel conduction, SnO2 based TFTs exhibited anomalous p-type conductivity. Integration of these n- and p-type devices resulted in complementary inverter with a gain of 11. (C) 2008 American Institute of Physics.
Development and Electrical Investigation of Through Glass Via and Through Si Via in 3D Integration
(2017-01-01)
Chang, Geng-Ming
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Lee, Shih-Wei
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Chang, Ching-Yun
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Chen, Kuan-Neng
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電子工程學系及電子研究所
In this research, an optimized process scheme for through glass via (TGV)/through silicon via (TSV) fabrication is proposed to solve the difficulty of copper (Cu) filling in TGV/TSV. Kelvin structure, daisy chain, and comb structure are fabricated for evaluating electrical performance. Comparison between TGV and TSV shows that the power loss and overall process steps (cost) of TGV is lower than TSV for 3D interconnect. Moreover, daisy chain structure at chip-level is fabricated and investigated on its reliability including thermal cycling and humidity test. Finally, TGV/TSV without voids and V-shape pits formed at the filler are successfully fabricated and demonstrated at chip-level with 50-mu m TGV/TSV and 200-mu m thinned wafers.
Development of Bumpless Stacking With Bottom-Up TSV Fabrication
(2017-04-01)
Lee, Shih-Wei
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A 3-D integration technology using bump less stacking based on a new bottom up Cu electroplating method without backside Cu chemical-mechanical planarization removal is presented in this paper. The approach successfully achieves via plating without thick Cu overburden by probing unique bottom electrodes for different I/O ports of TSV without additional steps in the conventional processes. The concepts and fabrication processes are described in detail. The results obtained from through silicon via (TSV) daisy chains show excellent electrical characteristics and good reliability in leakage current measurement. The proposed approach therefore has potential for low-cost via-last 3-D integration.
Electrical Testing Structure for Stacking Error Measurement in 3D Integration
(2016)
Lee, Shih-Wei
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Kuo, Shu-Chiao
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Chen, Kuan-Neng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel electrical test structure is proposed to inspect the stacking fault in 3D integration. This approach is one nondestructive analysis of the misalignment investigation. In order to determine the misalignment of wafer/chip stacking, the metal line pattern is designed to detect the direction and quantity of stacking fault. Testing circuit diagram is proposed and simulated for efficient measurement. In addition, different types of stacking fault including translation, rotation, and run out are discussed and formulated.
Fine-Feature Cu/In Interconnect Bonding Using Single Sided Heating and Chip-to-Wafer Bonding Technology
(2017-03-01)
Lee, Shih-Wei
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Chang, Ching-Yun
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Chang, Geng-Ming
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Chen, Kuan-Neng
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電子工程學系及電子研究所
A submicron-thick Cu/In bonding by using single sided heating approach has been successfully demonstrated on chip-to-wafer-level without antioxidant metal coating. The single sided heating approach can successfully prevent oxidation of Cu metal on the wafer during bonding. As compared with double sided heating method, a lower specific contact resistance can be obtained in single sided heating method. In addition, post-bonding annealing can further improve the bonding quality. Excellent electrical performances of reliability tests show a great potential for future highly dense interconnect.
High-performance single-layer polymer electrophosphorescent devices with polymer oxides
(2008)
Chen, Fang-Chung
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Chien, Shang-Chieh
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Lee, Shih-Wei
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光電工程學系
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顯示科技研究所
An enhanced power efficiency and a lower driving voltage of polymer electrophosphorescent devices have been demonstrated by blending poly(ethylene glycol) (PEG) into the active layer. The luminance efficiency of the device with Al cathode was up to 15.6 cd/A and the turn-on voltage was decreased to 5.6 V after the use of PEG. Further, the power efficiency was also improved to 5.0 lm/W. Moreover, similar improvement was also observed while Ca/Al or LiF/Ca/Al were used as the cathodes. The performance enhancement can be attributed to the interaction between Al and organic molecules with ethylene oxide groups, resulting in a better contact. (c) 2008 The Electrochemical Society.
Integrated Microprobe Array and CMOS MEMS by TSV Technology for Bio- Signal Recording Application
(2014-01-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Huang, Po-Tsang
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Chang, Chih-Wei
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Wu, Shang-Lin
Bio-signal probes that provide stable observation with high-quality signals are crucial for understanding how the brain works and how the neural signal transmits. Because bio-signals are weak and noisy, the length of the string connecting the sensor and Complementary Metal-Oxide-Semiconductor (CMOS) circuit significantly impacts biosignal quality. The collected weak signals from the sensor must pass through a series of interconnections and interfaces that introduce noise and lead to bulky packaged systems. This work uses through-silicon via (TSV) technology to connect the mu-probe array bio-sensor and CMOS circuit located on opposite sides of a chip for brain neural sensing applications. With the elimination of wire bonding and the reduction of the soldering, bio-signal quality can be significantly improved.
Polymer photovoltaic devices with highly transparent cathodes
(2008-12-01)
Chen, Fang-Chung
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Wu, Jyh-Lih
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Hsieh, Kuo-Huang
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Chen, Wen-Chang
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Lee, Shih-Wei
In this paper, we demonstrate semi-transparent polymer solar cells employing a transparent cathode configuration, made of cesium carbonate (Cs2CO3)/silver (Ag)/indium tin oxide (ITO), which exhibited high transmittance in the visible regime. The device performance of the semi-transparent devices was significantly improved after thermal post-annealing and incorporating an Al counter-electrode (CE) grid. Further, the short-circuit current density increased almost linearly with the incident light intensity, suggesting efficient charge collection ability of the transparent cathode. Overall, the semi-transparent polymer solar cell exhibits a remarkable power conversion efficiency of 2.09%. (C) 2008 Elsevier B.V. All rights reserved.
Polymer TSV Fabrication Scheme with Its Electrical and Reliability Test Vehicle
(2014)
Lee, Shih-Wei
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Shih, Jian-Yu
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Chuang, Ching-Te
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Hwang, Wei
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Chiou, Jin-Chern
In this research, a novel process scheme for polymer TSV fabrication is proposed to solve the difficulty of polymer liner formation in TSV technology. The corresponding structure shows great manufacturability to replace traditional fabrication approach. In addition, Kelvin structure of the daisy chain is designed for evaluating electrical performance and reliability. Moreover, daisy chain with dummy TSV is designed to verify the impact of TSV pitch on TSV fabrication by using electrical measurement. The reliability tests include thermal cycling and humidity test to verify the quality of proposed polymer TSV design. Finally, a void-free polymer TSV with uniform liner formation is successfully fabricated and demonstrated.
Polymer-Based Liner TSV Fabrication Scheme and Its Resistance Variation
(2017-07-01)
Lee, Shih-Wei
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Shih, Jian-Yu
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Chen, Kuo-Hua
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Chiu, Chi-Tsung
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Chen, Kuan-Neng
In this paper, a process scheme for polymer TSV fabrication is proposed to solve the difficulty of polymer liner formation in TSV technology. By using ring trench etching and BCB deposition in a vacuum environment, uniform BCB liner can be successfully fabricated. Electrical measurement by using Kelvin structure is completed to ensure the performance of fabrication. However, a new phenomenon causing tiny resistance changes with the arrangement of TSV is discovered during the measurement of TSV chain. In this research, this effect is discussed in detail by designing different design of experiment (DOE) to pursue good electrical connection and reduce the variance of delay property of each TSV. Based on statistical results, impacts of TSV manufacturing process variance are discussed and the guideline in high density TSV design is found.
Single Sided Heating Method for Chip-to-Wafer Bonding with Submicron Cu/In Interconnects
(2016)
Chang, Ching-Yun
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Lee, Shih-Wei
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Chang, Geng-Ming
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Chen, Kuan-Neng
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電子工程學系及電子研究所
In this research, a single sided heating method is developed to solve the issue of metal oxidation at bottom substrate without antioxidant metal coating in chip-to-wafer bonding. By using optimized bonding parameter, the bonding quality and electrical performance is better than double sided heating in chip-to-wafer bonding. With the help of Cu/In low temperature bonding and single sided heating approach, chip-to-wafer bonding is successfully developed. With the additional annealing process, the bonding duration of single sided heating bonding can be reduced to keep the cost down. Interconnects also maintain good electrical properties after reliability test such as TCT and unbiased HAST. These results prove that the single sided heating method is able to provide good bonding quality and reliability for chip-to-wafer bonding process.
Synthesis and characterization of heterocyclic conjugated polymers containing planar benzo[c]cinnoline and tetraazapyrene structures for organic field-effect transistor application
(2019-03-01)
Lee, Shih-Wei
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Chien, Shih-Hsuan
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Chen, Jyh-Chien
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Wang, Shih-Hao
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Wang, Lee-Yih
Heterocyclic conjugated polymers BZCTVT and TAPTVT containing benzo[c]cinnoline (BZC) and tetraazapyrene (TAP), respectively, were prepared by using Stille coupling polymerization in microwave reactor. BZC and TAP act as acceptors and thiophene-vinylene-thiophene (TVT) acts as donors. Alkylated thiophene is the linker between acceptor and donor. This is the first time that tetraazapyrene was incorporated into conjugated polymers. The films of BZCTVT and TAPTVT showed maximum absorption wavelength at 522 and 534 nm, respectively. From cyclic voltammertry measurement, TAPTVT and BZCTVT exhibited low LUMO (-3.61 and -3.47 eV) and HOMO (-5.64 and -5.63 eV) energy levels. Even though BZC and TAP were planar structures, BZCTVT and TAPTVT showed large dihedral angles between alkylated thiophene and TVT (10.8-22.6 degrees), and between alkylated thiophene and BZC and TAP (22.2-30.3 degrees) based on their simulated energy-minimized geometry. The bottom-gate, top-contact OFETs based on TAPTVT and BZCTVT exhibited only p-channel behavior with hole mobility of 4.63 x 10(-4) and 1.04 x 10(-4) cm(2) V-1 s(-1) and current on/off ratios greater than 10(4) after thermal annealing. Grazing incidence X-ray diffraction (GIXRD) patterns suggested that thin films of TAPTVT and BZCTVT preferred edge-on orientation.
Through-Silicon-Via-Based Double-Side Integrated Microsystem for Neural Sensing Applications
(2013-01-01)
Chang, Chih-Wei
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Huang, Po-Tsang
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Chou, Lei-Chun
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Wu, Shang-Lin
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Lee, Shih-Wei