Browsing by Author "Liao, CC"

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AC power loss and signal coupling in very large scale integration backend interconnects
(2006-04-01)
Chen, CC
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Kao, HL
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Liao, CC
;
Chin, A
;
McAlister, SP
Both the coupling and AC power losses in integrated circuit interconnects in the radio-frequency regime have been measured. The AC power loss decreases with decreasing length, decreasing spacing, and increasing inter metal dielectric (IMD) thickness of parallel metal lines. The unwanted signal coupling and cross-talk monotonically decrease with increasing spacing and decreasing length of the parallel metal lines. However, increasing the IMD thickness from 0.7 to 6 mu m improves the low frequency performance but not the maximum operation frequency. Using a high-resistivity Si (HRS) substrate the AC power loss is significantly reduced but is traded off with an increase in coupling loss. The most effective method of reducing both the AC power and coupling losses is the combined use of three dimensional (3D) integration and an HRS, which gives larger than 1-2 orders of magnitude improvement, up to 20 GHz.
Bias-temperature instability on fully silicided-germanided gates/high-k Al2O3CMOSFETs
(2005)
Liao, CC
;
Yu, DS
;
Cheng, CF
;
Chin, A
;
電子工程學系及電子研究所
We have studied bias-temperature instability (BTI) on fully nickel-silicided (NiSi) and germanided (NiGe) gates on high-k Al2O3 n metal oxide semiconductor field effect transistors (MOSFETs) and pMOSFETs, respectively. At an equivalent oxide thickness of 1.7 nm, the NiSi/Al2O3 pMOSFETs and NiGe/Al2O3 nMOSFETs have a comparable threshold voltage (V-t) change of -34 and 33 mV at 85&DEG; C and 10 MV/cm stress for 1 h. This result is different from the more severe negative BTI (NBTI) degradation measured in oxynitride pMOSFET than positive BTI (PBTI) in nMOSFET. The extrapolated maximum voltage for 10 years' lifetime is 1.16 and -1.12 V from NiSi-NiGe/Al2O3 complementary MOSFETs (CMOSFETs) that can barely meet the required 1 V operation with 10% safety margin. Further improvement is still required because the 1.8 nm oxynitride CMOSFETs have higher 10 years' lifetime operation voltages of 2.48 and -1.52 V for PBTI and NBTI, respectively. © 2005 The Electrochemical Society. All rights reserved.
Design of efficient high-gower diode-end-pumped TEMoo Nd : YVO4 laser
(2000)
Chen, YF
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Liao, CC
;
Lan, YP
;
Wang, SC
;
電子物理學系
A systematic investigation on a series of Nd:YVO4 crystals with different dopant concentrations is conducted to scale the diode-end-pumped laser performance to higher powers. The analysis reveals that lowering the dopant concentration linearly extends the fracture-limited pump power and the thermal shock parameter plays an important role in the estimation of the fracture-limited pump power: The thermal shock parameter in Nd:YVO4 crystals has been determined from the laser experiments, Based onthe analysis, we demonstrate a compact and efficient diode-end-pumped TEMoo laser with output power of 25.2-W for 52-W of incident pump power by use of a single YVO4 crystal with a Nd concentration of 0.3 at.%. In Q-switched operation 2 I-W of average power at a pulse repetition rate of 100 kHz and similar to 1.1-m pulse energy at a pulse repetition rate of 10 kHz were produced.
Determination of the Auger upconversion rate in fiber-coupled diode end-pumped Nd : YAG and Nd : YVO4 crystals
(2000-04-01)
Chen, YF
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Liao, CC
;
Lan, YP
;
Wang, SC
;
電子物理學系
An analytical model is developed to study the influence of the Auger upconversion process on the thermal loading under lasing and nonlasing conditions. With the developed model, Auger upconversion rates can be determined by comparing theoretical calculations with experimental results for the ratio of the thermal loading under lasing and nonlasing conditions. The upconversion rates obtained with the present method are compared with the results measured from the fluorescence decay experiment.
Efficient high-power diode-end-pumped TEM00 Nd : YVO4 laser
(1999-10-01)
Chen, YF
;
Huang, TM
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Liao, CC
;
Lan, YP
;
Wang, SC
We demonstrate a compact and efficient diode-end-pumped TEM00 laser with output power of 25.2 W for 52 W of incident pump power by use of a single YVO4 crystal with a Nd concentration of 0.3 at.%. In Q-switched operation 21-W of average power at a pulse repetition rate of 100 kHz and similar to 1.1-mJ pulse energy at a pulse repetition rate of 10 kHz were produced, At 10 kHz, the pulse width is around 10 ns and the peak power is higher than 100 kW.
Electrical characterization of Al2O3 on Si from thermally oxidized AlAs and Al
(1999-05-01)
Liao, CC
;
Chin, A
;
Tsai, C
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The scaling limit for VLSI gate oxide (SiO2) is 15-20 Angstrom that is determined by the large direct-tunneling leakage current. Further scaling to improve device performance can be obtained using a higher dielectric constant material. We have studied the Al2O3 to use as an alternative gate dielectric. To ensure good quality, Al2O3 is thermally oxidized from MBE-grown AlAs or Al on Si-substrates. Experimental results indicate that the leakage current from oxidized AlAs is larger than that from directly oxidized Al, which may be due to the weak As2O3 inside Al2O3. The leakage current of a 53 Angstrom Al2O3 is already lower than that of SiO2 with an equivalent oxide thickness of 21 Angstrom. (C) 1999 Published by Elsevier Science B.V. All rights reserved.
Electrical-stress effects and device modeling of 0.18-mu m RF MOSFETs
(2006-04-01)
Kao, HL
;
Chin, A
;
Liao, CC
;
Chen, CC
;
McAlister, SP
in this paper, a novel microstrip-line layout is used to make accurate measurements of the minimum noise figure (NFmin) of RF MOSFETs. A low NFmin of 1.05 dB at 10 GHz was directly measured for 16-finger 0.18-mu m MOSFETs, without de-embedding. Using an analytical expression for NFmin, we have developed a self-consistent dc current-voltage, S-parameter, and NF in model, where the simulated results match the measured device characteristics well, both before and after electrical stress.
High performance metal-gate/high-kappa, MOSFETs and GaAs compatible RF passive devices on Ge-on-Insulator tlechnology
(2004)
Chin, A
;
Kao, HL
;
Yu, DS
;
Liao, CC
;
Zhu, C
We propose and demonstrate a new VLSI structure using high performance metal-gate/high-kappa MOSFETs and high-Q RF passive devices on Ge-on- Insulator (GOI) platform. In additional to high RF performance passive devices on insulating Si formed by ion implantation. the metal-gate/(La)AiO(3)/GOI MOSFETs have 1.7-2.0X improved electron and hole mobility with the merits of minimizing interfacial reaction., high-kappa crystallization, Fermi-level pinning, and impurity diffusion due to low thermal budget of 500 degrees C RTA.
High quality La2O3 and Al2O3 gate dielectrics with equivalent oxide thickness 5-10 angstrom
(2000)
Chin, A
;
Wu, YH
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Chen, SB
;
Liao, CC
;
Chen, WJ
High quality La2O3 and Al2O3 are fabricated with EOT of 4.8 and 9.6 Angstrom, leakage current of 0.06 and 0.4A/cm(2) and D-it of both 3x10(10) eV(-1)/cm(2), respectively. The high K is further evidenced from high MOSFET's I-d and g(m) with low I-off Good SILC and Q(BD) are obtained and comparable with. SiO2. The low EOT is due to the high thermodynamic stability in contact with Si and stable after H-2 annealing up to 550 degrees C.
In0.52Al0.48As/InAs/InxAl1-xAs pseudomorphic HEMT's on InP
(1997-04-01)
Chin, A
;
Liao, CC
;
Tsai, C
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The dc and microwave performance of an InAs channel HEMT is reported. Room-temperature electron mobility as high as 20 200 cm(2)/Vs is measured, with a high carrier concentration of 2.7x10(12) cm(-2). DC extrinsic transconductance of 714 mS/mm is measured and a unity-current-gain cut-off frequency of 50 GHz is obtained for a 1.1-mu m gate length HEMT. The success of achieving superior Hall mobility and device performance is strongly dependent on the InxAl1-xAs buffer layer design that changes the lattice constant from lattice-matched In0.52Al0.48As to In0.75Al0.25As. The multiple In0.52Al0.48As/InAs monolayer superlattices buffer achieves the best performance as compared to the step-graded InxAl1-xAs and the uniform In0.75Al0.25As buffer.
Investigation of Si-doped p-type AlGaAs/GaAs, AlGaAs/InGaAs quantum well infrared photodetectors and multiquantum wells grown on (311)A GaAs
(1997-05-01)
Chin, A
;
Liao, CC
;
Chu, J
;
Li, SS
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電子工程學系及電子研究所
We have studied two Si-doped p-type quantum well infrared photodetectors (QWIPs) using AlGaAs/GaAs and AlGaAs/InGaAs grown on (3 1 1)A GaAs. The Si-doped AlGaAs/GaAs p-QWIP exhibits a symmetrical dark I-V characteristic at all the measured temperatures from 40 to 120 K. The strained p-type AlGaAs/InGaAs QWIP exhibits a slightly asymmetrical dark I-V characteristic, but is markedly less asymmetrical than that doped with beryllium. The slight asymmetry in dark I-V characteristic and the large blue-shift in responsivity spectra may be due to the thickness modulation observed from TEM and the red-shift of PL peak energy, where PL peak energies from (3 1 1)A AlGaAs/InGaAs multiple quantum wells are red-shifts of 7 and 22 meV to the side-by-side grown (1 0 0).
Low voltage lead titanate/Si one-transistor ferroelectric memory with good device characteristics
(2004-11-15)
Sun, CL
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Chen, SY
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Liao, CC
;
Chin, A
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材料科學與工程學系
We have developed one-transistor ferroelectric memory using lead titanate (PTO) as a gate dielectric directly formed on Si without any buffer layer. The PTO/Si metal-oxide-semiconductor field-effect transistor memory has shown a large threshold voltage shift of 1.6 V at only +/-4 V program/erase voltages. The corresponding good interface was achieved by lowering the anneal temperature to 450 degreesC. Besides the sharp capacitance change of 0.17 muF/V cm(2), it was also evidenced by the high mobility of 169 cm(2)/V s close to high-kappa HfO2. In addition, long retention >1000 s and endurance >10(11) stress cycles in the device suggested good memory characteristics. (C) 2004 American Institute of Physics.
Reducing AC power consumption by three-dimensional integration of Ge-on-insulator CMOS on 1-poly-6-metal 0.18 mu m Si MOSFETs
(2005)
Yu, DS
;
Liao, CC
;
Chen, CC
;
Lee, CF
;
Cheng, CF
We have used three-dimensional (3D) integration to reduce the ac power consumption in interconnects, which is the most severe issue beyond the dc power arising from the gate dielectric leakage current. From a direct calculation of the ac power consumption using an electromagnetic method, we show that both the ac power consumption and maximum operation frequency can be improved by integrating an additional integrated circuit layer. The 3D integration was realized by Ge-on-insulator (GOI) complementary metal oxide semiconductor field effect transistors (CMOSFETs) on 1-poly-6-metal (1P6M) 0.18 mu m Si devices, where little performance degradation was measured in the lower layer 0.18 mu m Si MOSFETs, due to the inherent low thermal budget (500 degrees C rapid thermal anneal) of the GOI processing. The drive current of the 3D GOI n- and p-MOSFETs was more than double that of the control Si devices, providing another advantage of the approach. (c) 2005 The Electrochemical Society. All rights reserved.
The copper contamination effect of Al2O3 gate dielectric on Si
(2004)
Liao, CC
;
Cheng, CF
;
Yu, DS
;
Chin, A
;
電子工程學系及電子研究所
We have studied the Cu contamination effect on 4.2 nm thick Al2O3 metal-oxide semiconductor (MOS) capacitors with an equivalent-oxide thickness (EOT) of 1.9 nm. In contrast to the large degradation of gate oxide integrity of control 3.0 nm SiO2 MOS capacitors contaminated by Cu, the 1.9 nm EOT Al2O3 MOS devices have good Cu contamination resistance with only small degradation of gate dielectric leakage current, charge-to-breakdown, and stress-induced leakage current. This strong Cu contamination resistance is similar to oxynitride (with high nitrogen content), but the Al2O3 gate dielectric has the advantage of higher K value and lower gate dielectric leakage current. (C) 2004 The Electrochemical Society.
The effect of IrO2-IrO2-Hf-LaAlO3 gate dielectric on the bias-temperature instability of 3-d GOI CMOSFETs
(2005-06-01)
Yu, DS
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Liao, CC
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Cheng, CF
;
Chin, A
;
Li, MF
We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-κ/Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 μ m CMOSFETs. The devices used IrO2-IrO2-Hf dual gates and a high-κ LaAlO3 gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-κ/GOI p-and n-MOSFETs displayed threshold voltage (V-t) shifts of 30 and 21 mV after 10 MV/cm, 85 &DEG; C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-κ-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.
Three-dimensional metal gate-high-kappa-GOI CMOSFETs on 1-poly-6-metal 0.18-mu m Si devices
(2005-02-01)
Yu, DS
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Chin, A
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Liao, CC
;
Lee, CF
;
Cheng, CF
We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-Insulator (GOI) CMOSFETs above 0.18-mum Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO3-GOI p-MOSFETs and IrO2-Hf-LaAlO3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm(2)/Vs respectively, without depredating the underneath 0.18-mum Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.
Very high kappa and high density TiTaO MIM capacitors for analog and RF applications
(2005)
Chiang, KC
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Chin, A
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Lai, CH
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Chen, WJ
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Cheng, CF
For the first time, high density (10.3 fF/mu m(2)), low voltage linearity (alpha = 89 ppm/V-2) and small leakage current (1.2 x 10(-8) A/cm(2) or 5.8 fA/[pF circle V] at 2V) meet all the ITRS requirements of analog capacitor at year 2018. These are achieved by novel high-kappa TiTaO (kappa = 45) and high work-function Ir capacitor, which further improve to very high 23 fF/mu m(2) density and low 81 ppm/V-2 linearity for higher speed analog/RF ICs at 1 GHz, using the fast a decay mechanism with increasing frequency.