Browsing by Author "Liu, Sally"

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A Novel Transmission-Line Deembedding Technique for RF Device Characterization
(2009-12-01)
Cho, Hsiu-Ying
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Huang, Jiun-Kai
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Kuo, Chin-Wei
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Liu, Sally
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Wu, Chung-Yu
A novel transmission-line deembedding technique is presented in this paper. With this technique, the left- and right-side ground-signal-ground probe pads can be extracted directly using two transmission-line test structures of length L and 2L. An additional through structure is designed using via-stack deembedding, which is unique among current deembedding methods. The advantages of the proposed method include the following: 1) smaller silicon area; 2) discontinuity between the pad and interconnect; 3) substrate coupling and contact effects; and 4) employment of via-stack deembedding. The proposed novel methodology is a great breakthrough in the area of ultrahigh-frequency deembedding and should enable more accurate RF models to be developed. In the proposed methodology, intrinsic slow-wave CPW transmission-line structures are placed on the interlevel metallization layers, as they are the most appropriate RF device for cascade-based deembedding method involving the via-stack deembedding technique. Experimental results have demonstrated that attenuation loss and wavelength can be optimized by changing the metal density and the position of the metal layer on the floating shields. Both measurement and electromagnetic-wave simulations were performed up to 50 GHz. With a shortened wavelength, a reduction in silicon area of more than 66% can be achieved by using optimized slot-type floating shields.
High performance band-pass filter embedded into SoCs using VLSI backend interconnects and high resistivity silicon substrate
(2006)
Chen, C. C.
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Chin, Albert
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Yang, M. T.
;
Liu, Sally
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電子工程學系及電子研究所
High performance band-pass filters are demonstrated on VLSI incorporating interconnects and high resistivity substrate. The resonating frequency of this coupled-line filter increases not only with the increasing spacing-gap but also with increasing IDM thickness. This band-pass filter, low insertion loss and wide bandwidth characteristics, are suitable for the advanced wireless system. The established equivalent circuit model for this band-pass filter corresponds with the measured results and provides effectively RIF passive components embedded into system-on-a-chips.
High-Performance Slow-Wave Transmission Lines With Optimized Slot-Type Floating Shields
(2009-08-01)
Cho, Hsiu-Ying
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Yeh, Tzu-Jin
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Liu, Sally
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Wu, Chung-Yu
;
交大名義發表
A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide substrate shielding and to shorten the electromagnetic (EM) propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length (SL), strip spacing (SS), and metal layer position of the slot-type floating shields. Wavelength shortening needs to be achieved with a tradeoff between slow-wave effect and attenuation loss. The slot-type floating shields with different SLs, SSs and metal layer positions are analyzed. It is concluded that minimum SL provides the most optimal result. A design guideline can be established to enable circuit designers to reach the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45-nm CMOS process technology. Both measurement and EM waves simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half-or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, which is improved by a factor of more than 9, and a better quality factor, which is improved by a factor of more than 6, as compared to conventional transmission lines.
Investigation of anomalous inversion C-V characteristics for long-channel MOSFETs with leaky dielectrics: Mechanisms and reconstruction
(2008-02-01)
Lee, Wei
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Su, Pin
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Su, Ke-Wei
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Chiang, Chung-Shi
;
Liu, Sally
This paper investigates anomalous inversion capacitance-voltage (C-V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C-V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (R-ii). The concept of R-ii has been validated by segmented BSIM4/SPICE simulation. Our reconstructed C-V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method and agree well with the North Carolina State University-CVC simulation results. The intrinsic input resistance dominates the overall gate-current-induced debiasing effect (similar to 95% for L = 20 mu m) and can be extracted directly from the I-V characteristics. Due to its simplicity, our proposed R-ii approach may provide an option for regular process monitoring purposes.
Investigation of inversion capacitance-voltage reconstruction for metal oxide semiconductor field effect transistors with leaky dielectrics using BSIM4/SPICE and intrinsic input resistance model
(2007-04-01)
Lee, Wei
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Su, Pin
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Su, Ke-Wei
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Chiang, Chung-Shi
;
Liu, Sally
This paper presents an inversion capacitance-voltage (C-V) reconstruction method for long-channel metal oxide semiconductor field effect transistors (MOSFETs) using the BSIM4/SPICE and the intrinsic input resistance (R-ii) model. The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Since the Rii model is scalable with V-Gs and L, our R-ii approach is physically accurate. Due to its simplicity, this method may provide an option for regular process monitoring purposes.
Modeling the well-edge proximity effect in highly scaled MOSFETs
(2006-11-01)
Sheu, Yi-Ming
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Su, Ke-Wei
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Tian, Shiyang
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Yang, Sheng-Jier
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Wang, Chih-Chiang
The well-edge proximity effect caused by ion scattering during implantation in highly scaled CMOS technology is explored from a physics and process perspective. Technology computer-aided design (TCAD) simulations together with silicon wafer experiments have been conducted to investigate the impact of this effect. The ion scattering model and TCAD simulations provided a physical understanding of how the internal changes of the MOSFETs are formed. A new compact model for SPICE is proposed using physics-based understanding and has been calibrated using experimental silicon test sets.
OPTIMIZATION AND MODELING FOR MOS VARACTORS IN 65 nm LOW-POWER MIXED-SIGNAL/RADIO-FREQUENCY TECHNOLOGY
(2009-09-01)
Chen, Chia Chung
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Jiang, Meshon
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Chang, Li Ming
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Yeh, Tzu Jin
;
Liu, Feng Ming
CMOS technology scaling opens tip the possibility of designing variable capacitors based oil a metal oxide semiconductor (MOS) structure with improved tuning range and quality factor. In this work, the high Q-factor 24 and 21, wide timing ratio 45% and 36% can be achieved by 65 nm low power technology n+/n-well and p+/p-well MOS varactor up to 10 GHZ, respectively. Meanwhile, the equivalent circuit model, to model intrinsic and extrinsic parameters of MOS varactor, also have demonstrated that parasitic resistance is a main issue to dominate Q-factors, and the measured flicker noise result of MOS varactor is directly dependant on gate leakage current. (C) 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2119-2121. 2009; Published online in Wiley InterScience (www.intescience.wiley.com). DOI 10.1002/mop.24567
Reproducing subthreshold characteristics of metal-oxide-semiconductor field effect transistors under shallow trench isolation mechanical stress using a stress-dependent diffusion model
(2006-08-01)
Sheu, Yi-Ming
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Yang, Sheng-Jier
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Wang, Chih-Chiang
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Chang, Chih-Sheng
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Chen, Ming-Jer
N-channel metal-oxide-semiconductor field effect transistors (MOSFETs) with a lightly doped well exhibit subthreshold current versus voltage (I-V) characteristics that are sensitive to shallow trench isolation (STI) mechanical stress. Such striking dependencies offer the opportunity to validate a proposed two-dimensional (2D) process model that relates the impurity diffusion to the mechanical stress throughout the substrate. With the assistance of sophisticated process/device simulations, the model appears to satisfactorily reproduce subthreshold I-V characteristics for different active area lengths and different substrate biases. The stress-dependent point defect equilibrium concentration and diffusion model are also implemented to evaluate the stress effect on transient enhanced diffusion.
Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack
(2016-04-01)
Liu, Chien
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Chen, Ping-Guang
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Xie, Meng-Jie
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Liu, Shao-Nong
;
Lee, Jun-Wei
The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10 mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2V switching voltage) to realize next-generation state-of-the-art devices. (C) 2016 The Japan Society of Applied Physics
Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack
(2016-04)
Liu, Chien
;
Chen, Ping-Guang
;
Xie, Meng-Jie
;
Liu, Shao-Nong
;
Lee, Jun-Wei
The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10 mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2V switching voltage) to realize next-generation state-of-the-art devices. (C) 2016 The Japan Society of Applied Physics