Browsing by Author "Lu, Ching-Sen"

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Analysis of Oxide Trap Characteristics by Random Telegraph Signals in nMOSFETs With HfO2-Based Gate Dielectrics
(2016-04)
Chen, Ching-En
;
Chang, Ting-Chang
;
You, Bo
;
Tsai, Jyun-Yu
;
Lo, Wen-Hung
This letter investigates the oxide trap properties in n-channel metal-oxide-semiconductor field-effect transistors with HfO2 and Hf(1-x)ZrxO(2)/metal gate-stacks by an analysis of random telegraph signals. According to the multiphonon emission theory, the extracted relaxation energies show gate voltage dependence in devices with HfO2-based stacks. This dependence results from the different strengths of vibrations of the nearest neighbor Hf atoms of the oxygen vacancy in the immediate vicinity of the oxide trap. Furthermore, this dependence also induces an abnormal gate voltage dependence in terms of the activation energy required for electron capture. These results are confirmed by comparisons between two HfO2-based devices (HfO2 and Hf(1-x)ZrxO(2)).
Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks
(2014-10-06)
Tsai, Jyun-Yu
;
Chang, Ting-Chang
;
Chen, Ching-En
;
Ho, Szu-Han
;
Liu, Kuan-Ju
This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks. (C) 2014 AIP Publishing LLC.
Impacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained n-channel metal-oxide-semiconductor field-effect transistors with SiN capping
(2007-03-19)
Lu, Ching-Sen
;
Lin, Horng-Chih
;
Huang, Jian-Ming
;
Lee, Yao-Jen
;
電子工程學系及電子研究所
Characteristics of n-channel metal-oxide-semiconductor field-effect transistors with SiN capping were investigated in this work. Although the SiN capping could dramatically enhance the carrier mobility and thus the device drive current, the resistance to hot-carrier degradation is compromised as well, owing to the large amount of hydrogen contained in the SiN layer which may diffuse into the channel region during the process. To eliminate this shortcoming, the insertion of an ultrathin (10 nm) polycrystalline-silicon buffer layer between the gate and the SiN capping was proposed and demonstrated to restore the hot-carrier reliability of the devices without compromising the current enhancement due to the SiN capping. (c) 2007 American Institute of Physics.
Impacts of low-pressure chemical vapor deposition-SiN capping layer and lateral distribution of interface traps on hot-carrier stress of n-channel metal-oxide-semiconductor field-effect-transistors
(2007-04-01)
Lu, Ching-Sen
;
Lin, Horng-Chih
;
Huang, Jian-Ming
;
Lu, Chia-Yu
;
Lee, Yao-Jen
The characteristics of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) with a SiN capping layer were investigated in this study. Although the incorporation of the SiN capping layer markedly enhanced the carrier mobility and thus the drive current of the fabricated devices, the resistance to hot-carrier degradation was sacrificed, owing to the high content of hydrogen in the SiN layer that might diffuse to the channel region during the process. Even if the SiN layer was removed and the channel strain was released later, the hot-carrier degradation was severer than that in devices without SiN capping. Finally, the lateral distribution of generated interface states due to hot-carrier stress was also investigated in this study.
Impacts of precursor flow rate and temperature of PECVD-SiN capping films on strained-channel NMOSFETs
(2007)
Lu, Ching-Sen
;
Lin, Horng-Chih
;
Lee, Yao-Jen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
Impacts of SiN deposition parameters on n-channel metal-oxide-semiconductor field-effect-transistors
(2008-10-01)
Lu, Ching-Sen
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Although the incorporation of a SiN capping layer could dramatically enhance device performance, the accompanying hydrogen species contained in the capping layer may aggravate hot-carrier reliability. In order to alleviate this shortcoming, we vary the precursor flow conditions and deposition temperature of SiN film during plasma-enhanced chemical vapor deposition (PECVD) and study their impacts on the device performance and reliability. We found that SiN film with higher nitrogen content depicts larger tensile stress and therefore better mobility. More importantly, the resistance to hot-carrier degradation is also improved by increasing N-2 gas flow rate and deposition temperature because of less hydrogen diffusion from the capping layer. (C) 2008 Elsevier Ltd. All rights reserved.
Improved hot carrier reliability in strained-channel NMOSFETS with TEOS buffer layer
(2007)
Lu, Ching-Sen
;
Lin, Horng-Chih
;
Lee, Yao-Jen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
Improved NBTI in SiN-capped PMOSFETs with ultra-thin HfO2 buffer
(2007)
Lu, Ching-Sen
;
Lin, Horng-Chih
;
Chen, Ying-Hung
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
Although a compressive SiN capping could effectively boost the drive current of PMOS devices, it may concomitantly worsen the NBTI characteristics owing to the high hydrogen content in the SiN layer which might diffuse to the channel region during processing. To address this issue, inserting a thin 3nm HfO2 buffer layer between the gate and SiN capping is proposed and demonstrated to improve NBTI reliability without sacrificing the performance enhancement by SiN capping.
Improvement of negative-bias-temperature instability in SiN-capped p-channel metal-oxide-semiconductor field-effect transistors using ultrathin HfO2 buffer layer
(2007)
Lu, Ching-Sen
;
Horng-Chih, Lin
;
Lee, Yao-Jen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Characteristics of p-channel SiN-capped metal-oxide-semiconductor field-effect transistors (PMOSFETs) with a thin HfO2 buffer layer were investigated. The compressive strain in the channel was deliberately induced in this study by a SiN capping layer over the gate using plasma-enhanced chemical vapor deposition (PECVD). Although a compressive SiN capping effectively boosts the drive current of PMOSFET devices, its presence also worsens the negative bias temperature instability (NBTI) characteristics due to the high hydrogen content in the SiN layer, which could diffuse into the channel region during the deposition process. To address this issue, the insertion of a 3 nm thick HfO2 buffer layer between the gate and SiN capping is proposed and demonstrated to improve NBTI reliability without sacrificing the device performance enhancement. (c) 2007 The Electrochemical Society.
Investigation of abnormal negative threshold voltage shift under positive bias stress in input/output n-channel metal-oxide-semiconductor field-effect transistors with TiN/HfO2 structure using fast I-V measurement
(2014-03-17)
Ho, Szu-Han
;
Chang, Ting-Chang
;
Lu, Ying-Hsin
;
Chen, Ching-En
;
Tsai, Jyun-Yu
This letter investigates abnormal negative threshold voltage shifts under positive bias stress in input/output (I/O) TiN/HfO2 n-channel metal-oxide-semiconductor field-effect transistors using fast I-V measurement. This phenomenon is attributed to a reversible charge/discharge effect in pre-existing bulk traps. Moreover, in standard performance devices, threshold-voltage (V-t) shifts positively during fast I-V double sweep measurement. However, in I/O devices, V-t shifts negatively since electrons escape from bulk traps to metal gate rather than channel electrons injecting to bulk traps. Consequently, decreasing pre-existing bulk traps in I/O devices, which can be achieved by adopting HfxZr1-xO2 as gate oxide, can reduce the charge/discharge effect. (C) 2014 AIP Publishing LLC.
Optimization of SiN film by varying precursor flow conditions and its impacts on strained channel NMOSFETs
(2007)
Lu, Ching-Sen
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, we investigate the effect of precursor flow conditions on the properties of the SiN film deposited by PECVD, and the related impacts on the device performance as well as hot-carrier reliability of NMOSFETs. We found that SiN film with higher nitrogen content possess larger tensile stress and thus higher on-current. Moreover, lower hydrogen contained in the SiN boosts the immunity to hot-carrier stress. Both demands can be fulfilled by increasing the N(2) gas flow rate during SiN deposition. The lateral distribution of interface state generation after hot-carrier stress was also investigated.
The Impact of Pre/Post-metal Deposition Annealing on Negative-Bias-Temperature Instability in HfO2 Stack p-Channel Metal-Oxide-Semiconductor Field Effect Transistors
(2015-01-01)
Lu, Ying-Hsin
;
Chang, Ting-Chang
;
Ho, Szu-Han
;
Chen, Ching-En
;
Tsai, Jyun-Yu
This study investigates the impact of pre/post-metal deposition annealing on negative-bias-temperature instability (NBTI) in HfO2 stack p-channel metal-oxide-semiconductor field effect transistors (MOSFETs). In the initial electrical characteristics, the most apparent difference is threshold voltage (V-th) resulting from the work-function difference between the gate material and the semiconductor. Furthermore, fast I-V measurements indicate that the device with post-metal deposition annealing shows more degradation of V-th in NBTI, which originates from the more nitrogen interstitial defects in HfO2. This phenomenon is confirmed to be due to the process-related pre-existing defects by an analysis of double sweep fast I-V measurements. (c) 2015 The Electrochemical Society. All rights reserved.