Browsing by Author "Luo, Zhicong"

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A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18-mu m 1.8-V/3.3-V Low-Voltage CMOS Process
(2017-10-01)
Luo, Zhicong
;
Ker, Ming-Dou
;
Yang, Tzu-Yi
;
Cheng, Wan-Hsueh
;
電子工程學系及電子研究所
A new digitally dynamic power supply technique for 16-channel 12-V-tolerant stimulator is proposed and realized in a 0.18-mu m 1.8-V/3.3-V CMOS process. The proposed stimulator uses four stacked transistors as the pull-down switch and pullup switch to withstand 4 times the nominal supply voltage (4 x VDD). With the dc input voltage of 3.3 V, the regulated threestage charge pump, which is capable of providing 11.3-V voltage at 3-mA loading current, achieves dc conversion efficiency of up to 69% with 400-pF integrated capacitance. Power consumption is reduced by implementing the regulated charge pump to provide a dynamic dc output voltage with a 0.5-V step. The proposed digitally dynamic power supply technique, which is implemented by using a p-type metal oxide semiconductor (PMOS) inverter with pulldown current source and digital controller, greatly improves the power efficiency of a system. The silicon area of the stimulator is approximately 3.5 mm(2) for a 16-channel implementation. The functionalities of the proposed stimulator have been successfully verified through animal test.
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
(2018-11-01)
Cheng, Cheng-Hsiang
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Tsai, Ping-Yuan
;
Yang, Tzu-Yi
;
Cheng, Wan-Hsueh
;
Yen, Ting-Yang
A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 mu V-rms and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5-3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18-mu m CMOS technology and occupies 25 mm(2). Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression.
A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bidirectional Data Telemetry for Real-Time Human Epileptic Seizure Control
(2017-01-01)
Cheng, Cheng-Hsiang
;
Tsai, Ping-Yuan
;
Yang, Tzu-Yi
;
Cheng, Wan-Hsueh
;
Yen, Ting-Yang
This paper presents a 16-channel closed-loop neuromodulation SoC for human seizure control. The SoC includes a 16-ch signal acquisition unit, a bio-signal processor, a 16-ch adaptive stimulator, and wireless telemetry. The signal acquisition unit achieves 3.78 NEF and shares electrodes with stimulator. The seizure detection latency is 0.76s and delivered 0.5-3mA biphasic current stimulation. The SoC is powered wirelessly and bidirectional data telemetry is realized through the same pair of coils in 13.56MHz.
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications
(2018-06-01)
Luo, Zhicong
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
;
Department of Electronics Engineering and Institute of Electronics
A high-voltage-tolerant and power-efficient stimulator with adaptive power supply is proposed and realized in a 0.18- mu m 1.8-V/3.3-V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent issues of electrical overstress and gate-oxide reliability in low-voltage transistors. The on-chip high-voltage generator uses a pulse-skip regulation scheme to generate a variable dc supply voltage for the stimulator by detecting the headroom voltage on the electrode sites. With a dc input voltage of 3.3 V, the onchip high-voltage generator provides an adjustable dc output voltage from 6.7 to 12.3 V at a step of 0.8 V, which results in a maximal system power efficiency of 56% at a 2400-mu A stimulus current. The charge mismatch of the stimulator is down to 1.7% in the whole stimulus current range of 200-3000 mu A. The in vivo experiments verified that epileptic seizures could be suppressed by the electrical stimulation provided by the proposed stimulator. In addition, the reliability measurements verified that the proposed stimulator is robust for electrical stimulation in medical applications.
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process
(2016-12)
Luo, Zhicong
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a 4 x V-DD neuro-stimulator in a 0.18-mu m 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000-mu A biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 mu A) The residual average dc current is less than 6.6 nA after shorting operation.
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process
(2019-09-01)
Luo, Zhicong
;
Yu, Li-Chin
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A wide-output, power-efficient, high-voltage charge pump with a variable number of stages is proposed and realized in a 0.18 mu m 1.8 V/3.3 V CMOS process. The proposed stage selection circuit changes the node voltages in the charge pump circuit in a domino effect to ensure that the maximum voltages across the terminals of each transistor are kept within the normal supply voltage (V-DD). The stage selection circuit is able to bypass or activate each stage of the charge pump. Experimental results indicate that the proposed charge pump provides a wide-output voltage range: 3.3-12.6 V from a 3.3 V input source. A peak efficiency of 70% was reached in the charge pump at a current loading of 3.5 mA. By selecting the optimal number of active stages, the overall power efficiencies can be greater than 60% under the output voltages of 4.8 V, 8.1 V, and 10.8 V, respectively. By optimizing the number of active stages, an increase of up to 35% power efficiency can be gained. The proposed stage selection circuit is applicable to other on-chip wide-output charge-pumps.
Design of High-Voltage-Tolerant Level Shifter in Low Voltage CMOS Process for Neuro Stimulator
(2016)
Luo, Zhicong
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Ker, Ming-Dou
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生醫電子轉譯研究中心
;
Biomedical Electronics Translational Research Center
A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-mu m CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (V-DD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the coupling capacitors and the cross-coupled transistor pairs. Electrical overstress and the gate-oxide reliability issues can be fully eliminated because all transistors in the proposed level shifter are operating within the safe voltage range.
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
(2017-03-01)
Luo, Zhicong
;
Ker, Ming-Dou
;
Cheng, Wan-Hsueh
;
Yen, Ting-Yang
;
電子工程學系及電子研究所
A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18-mu m 1.8-V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple charge pump and the expressions for the charging current are described in detail. The experiment results show that the charging current ripples are reduced by a factor of three through using the proposed new clocking scheme. The voltage ripples in the power supply line, which is connected with the charge pump input, are also smoothed greatly as the filter circuit does. The proposed scheme is used to decrease the smoothing capacitance in the power line of charge pump for reducing the size of implantable devices in biomedical application. In addition, the power efficiency is improved. The proposed cross-couple charge pump can provide 10.5-V output voltage with 3.5-mA output current, and the power efficiency of the charge pump can be up to 69%.