Design of High-Voltage-Tolerant Level Shifter in Low Voltage CMOS Process for Neuro Stimulator

Abstract

A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-mu m CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (V-DD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the coupling capacitors and the cross-coupled transistor pairs. Electrical overstress and the gate-oxide reliability issues can be fully eliminated because all transistors in the proposed level shifter are operating within the safe voltage range.