Design of High-Voltage-Tolerant Level Shifter in Low Voltage CMOS Process for Neuro Stimulator

dc.citation.woscount	0	en_US
dc.contributor.author	Luo, Zhicong	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.department	生醫電子轉譯研究中心	zh_TW
dc.contributor.department	Biomedical Electronics Translational Research Center	en_US
dc.date.accessioned	2017-04-21T06:48:21Z
dc.date.available	2017-04-21T06:48:21Z
dc.date.issued	2016	en_US
dc.description.abstract	A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-mu m CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (V-DD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the coupling capacitors and the cross-coupled transistor pairs. Electrical overstress and the gate-oxide reliability issues can be fully eliminated because all transistors in the proposed level shifter are operating within the safe voltage range.	en_US
dc.identifier.isbn	978-1-4673-8900-6	en_US
dc.identifier.issn	2472-467X	en_US
dc.identifier.journal	2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/136454
dc.identifier.wosnumber	WOS:000386900400038	en_US
dc.language.iso	en_US	en_US
dc.title	Design of High-Voltage-Tolerant Level Shifter in Low Voltage CMOS Process for Neuro Stimulator	en_US
dc.type	Proceedings Paper	en_US

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