Browsing by Author "Ni, Chia-Lung"

Now showing 1 - 11 of 11

800V Ultra-High-Voltage Start-up Mechanism for Pre-regulator in Power Factor Correction (PFC) Controller
(2011)
Chen, Chi-Lin
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Tsai, Jen-Chieh
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Chen, Yi-Ting
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Ni, Chia-Lung
;
Chen, Chun-Yen
The on-chip 800V ultra-high-voltage (UHV) start-up mechanism was introduced in this paper. Using the UHV start-up mechanism can minimize the current leakage at the AC input and remove the need of external start-up resistor and capacitor. As a result, the standby current can be decreased to improve the efficiency of AC-DC systems. Furthermore, the zero current detection (ZCD) circuit was used here to ensure the work of the pre-regulator. An inductance coil will detect the primary inductance current and reflect the voltage, which is detected by ZCD circuit to provide the energy to the pre-regulator. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Certainly, high efficiency of 95% can be ensured at the output power of 50W.
92% High Efficiency and Low Current Mismatch Interleaving Power Factor Correction Controller With Variable Sampling Slope and Automatic Loading Detection Techniques
(2013-11-01)
Su, Yi-Ping
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Chen, Chun-Yen
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Ni, Chia-Lung
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Kang, Yu-Chai
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Chen, Yi-Ting
This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92% over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-mu m 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180 W and a high efficiency of 95% at an output power of 180 W.
Automatic Loading Detection (ALD) Technique for 92% High Efficiency Interleaving Power Factor Correction (PFC) Over a Wide Output Power of 180W
(2012)
Tsai, Jen-Chive
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Chen, Chun-Yen
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Chen, Yi-Ting
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Ni, Chia-Lung
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Su, Yi-Ping
the proposed automatic loading detection (ALD) technique keeps high efficiency in interleaving power factor correction (PFC) over a wide load range. With the advantages of small input/output filter and output ripple in the interleaving mechanism, the improved efficiency by the ALD technique at light loads due to reduced switching loss can be widely used in the adapter of portable electronics. The ALD technique can calculate the power by the detection of peak input voltage to reduce the switching loss since the slave channel can be completely turned off for power saving at light loads. Therefore, the boundary control mode (BCM) control can simultaneously provide high power and keep high conversion efficiency both at light and heavy loads. The highly integrated PFC controller fabricated in TSMC 800V UHV process shows high efficiency of 92% over a wide output power of 180 W.
Boundary Conduction Mode Controlled Power Factor Corrector With Line Voltage Recovery and Total Harmonic Distortion Improvement Techniques
(2014-07-01)
Su, Yi-Ping
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Ni, Chia-Lung
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Chen, Chun-Yen
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Chen, Yi-Ting
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Tsai, Jen-Chieh
The proposed line voltage recovery (LVR) and the total harmonic distortion improvement (THDI) technique improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range in boundary conduction mode controlled power factor corrector (PFC). The LVR detects the input line root-mean-square voltage to generate the digital equivalent code to the THDI for optimizing the THD by tuning the on-time value at different line voltages. In addition, the LVR and the THDI provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC controller can keep high PF and low THD over a wide line voltage. Experimental results demonstrate that the peak PF value is 0.998 and the minimum THD is 1.7% by the test circuit fabricated in a TSMC 800-V ultrahigh-voltage process with the universal line voltage range of 90-264 V.
High-PF and Ultra-Low-THD Power Factor Correction Controller by Sinusoidal-Wave Synthesis and Optimized THD Control
(2013)
Chang, Chih-Wei
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Ni, Chia-Lung
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Tsai, Jen-Chieh
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Chen, Yi-Ting
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Chen, Chun-Yen
the proposed sinusoidal-wave synthesis (SWS) and the optimized THD control (OTC) improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range. The SWS detects the input line root-mean-square (rms) voltage to generate the digital equivalent code to the OTC for optimizing the THD by tuning the on-time value. Besides, the SWS and the OTC provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC converter can keep high PF and low THD over a wide line voltage. Experimental results demonstrate the PF is higher than 0.99 and the THD is 1.7% at V-AC of 90 - 110V by the test circuit fabricated in TSMC 800V UHV process.
Perturbation On-time (POT) Control and Inhibit Time Control (ITC) in Suppression of THD of Power Factor Correction (PFC) Design
(2011)
Tsai, Jen-Chieh
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Chen, Chi-Lin
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Chen, Yi-Ting
;
Ni, Chia-Lung
;
Chen, Chun-Yen
The paper presented the perturbation on-time (POT) control technique to suppress the total harmonic distortion (THD) to improve the performance of the power factor correction (PFC) in the AC-DC converter. Simultaneously, it can improve the efficiency through the proposed inhibit time control (ITC) mechanism at low AC input voltage. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Besides, high efficiency of 95% can be ensured at the output power of 90W.
Perturbation On-Time (POT) Technique in Power Factor Correction (PFC) Controller for Low Total Harmonic Distortion and High Power Factor
(2013-01-01)
Tsai, Jen-Chieh
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Chen, Chi-Lin
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Chen, Yi-Ting
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Ni, Chia-Lung
;
Chen, Chun-Yen
The proposed perturbation on-time technique suppresses total harmonic distortion (THD) and, thus, improves the power factor in the power factor correction (PFC) controller. Besides, the adaptive control of the minimum off time by the proposed inhibit time control can improve efficiency even at low ac input voltage. Therefore, highly integrated PFC converter fabricated in the TSMC 800-V ultrahigh voltage process can achieve low THD of 6%, high PF of 99%, and high efficiency of 95% at the output power of 90 W.
Time-Shift Current Balance Technique in Four-Phase Voltage Regulator Module with 90% Efficiency for Cloud Computing
(2015-03-01)
Su, Yi-Ping
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Chen, Wei-Chung
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Huang, Yu-Ping
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Chen, Chun-Yen
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Ni, Chia-Lung
Four power stages for voltage regulator module (VRM) are adopted to provide high current driving capability and low output ripple in cloud computing. Thus, the time-shift current balance (TSCB) technique is proposed to achieve high performance power supply for servers. In addition, the power request, which includes the number of active phases and voltage identification, is acknowledged by servers for high driving capability during high throughput and high efficiency during standby mode. Furthermore, to equally distribute the current in each phase, the proposed TSCB technique in either voltage-mode or peak current-mode control improves the current balance performance and solves the stability problem. In the scale-down clouding computing prototype, the efficiency can be kept higher than 90% over a wide load current range of 2 A. In addition, the performance and operating frequency of the servers in stable operation are not limited by the VRM with the TSCB technique.
Triple Loop Modulation (TLM) for High Reliability and Efficiency in a Power Factor Correction (PFC) System
(2013-07-01)
Tsai, Jen-Chieh
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Ni, Chia-Lung
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Chen, Chi-Lin
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Chen, Yi-Ting
;
Chen, Chun-Yen
The proposed triple loop modulation (TLM) can ensure reliability of the power factor correction (PFC) system due to the improvement of transient response. In conventional design, low bandwidth of less than 20Hz that rejects ac source of 60/120 Hz coupling deteriorates system reliability in case of output load variation. Contrarily, the proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current to shorten transient response time. Besides, in the steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by the TLM. The test circuit fabricated in a VIS 500 V UHV laterally diffused metal-oxide-semiconductor transistor process demonstrates that the highly integrated PFC controller with the proposed TLM has high power factor of 99%, high efficiency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than in conventional PFC design with output load variation from 90 to 20W and vice versa.
Triple Loop Modulation (TLM) for High Reliability and Efficiency in Power Factor Correction (PFC) System
(2012)
Tsai, Jen-Chieh
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Ni, Chia-Lung
;
Chen, Chun-Yen
;
Chen, Yi-Ting
;
Chen, Chi-Lin
Reliability of the Power Factor Correction (PFC) system was improved by fast transient response using the proposed triple loop modulation (TLM). Low bandwidth of less than 20 Hz that rejects AC source of 60/120 Hz coupling deteriorated system reliability in case of output load variation. The proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current in order to shorten transient response time. In steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by TLM. The test circuit fabricated in VIS 500 V UHV LDMOS process demonstrated the performance of the highly-integrated PFC controller with the proposed TLM. Experimental results showed that the PFC system with TLM has high PF of 99%, high efficiency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than conventional PFC design with output load variation from 90W to 45 W and vice versa.
Variable Sampling Slope (VSS) and No-Deadtime Ramp Generator (NDRG) Techniques for Closed-Loop Interleaving Power Factor Correction (PFC) Design with Suppression of Current Mismatch
(2012)
Chen, Chun-Yen
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Peng, Ruei Hong
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Tsai, Jen-Chieh
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Kang, Yu-Chi
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Ni, Chia-Lung
the proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5 mu m 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.