Browsing by Author "Shih, Yi-Jia"

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A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid P/N Layer and Vertical Gate with Very High Ion/Ioff for 3D Stacked ICs
(2016)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Cheng, Chun-Hu
;
Shih, Yi-Jia
This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high I-on/I-off current ratio (> 10(9)), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.
Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off
(2015-11-02)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Wu, Yi-Kang
;
Shih, Yi-Jia
A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.
Improved Electrical Characteristics and Reliability of Multi-Stacking PNPN Junctionless Transistors Using Channel Depletion Effect
(2017-01-01)
Lin, Ming-Huei
;
Shih, Yi-Jia
;
Liu, Chien
;
Chiu, Yu-Chien
;
Fan, Chia-Chi
This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10(7). Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.
Improved Thermal Stability and Stress Immunity in Highly Scalable Junctionless FETs Using Enhanced-Depletion Channels
(2018-12-05)
Liu, Chien
;
Cheng, Chun-Hu
;
Lin, Ming-Huei
;
Shih, Yi-Jia
;
Hung, Yu-Wen
In this work, we report a novel multi-PNPN-channel junctionless transistor with short channel length of 60nm. The multi-PNPN junctionless transistor exhibits the larger drive current of > 1 mu A/mu m, the steeper turn-on switching of 77 mV/decade, and the higher on/off current ratio of > 10(7) than the hybrid PN channel device under the same gate overdrive. The improved performance is mainly attributed to the enhanced depletion effect of multi-PNPN channel to optimize the electric field modification of surface p-channel. The stronger immunity to constant-voltage stress is also obtained for multi-PNPN channel due to the lower lateral electric field near drain side to reduce the impact ionization ratio. (C) 2018 The Electrochemical Society.