Browsing by Author "Su, Chauchin"

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A 0.09 mu W Low Power Front-End Biopotential Amplifier for Biosignal Recording
(2012-10-01)
Tseng, Yuhwai
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Ho, Yingchieh
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Kao, Shuoting
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Su, Chauchin
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電子工程學系及電子研究所
This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 mu A, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 mu m CMOS technology with a core area of 0.77 X 0.36 mm(2). With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09 mu W, respectively.
A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters
(2012-05-01)
Ho, Yingchieh
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Su, Chauchin
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電機工程學系
;
電控工程研究所
;
Department of Electrical and Computer Engineering
This paper presents a 40-130 fJ/bit/ch on-chip data link design under a 0.1-0.3V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a -V-DD to 2V(DD) swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8-100 Mbps, and the energy consumption is 40-123 fJ per bit under 0.1-0.3 V-DD.
A 0.5V/22 mu W Low Power Transceiver IC for Use in FSC Intra-body Communication System
(2016)
Tseng, Yuhwai
;
Lin, Tinyou
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Yau, Songwen
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Ho, Yingchieh
;
Su, Chauchin
This paper presents an integrated transciver chip for use in electro-static coupling intra body communication. A simplified circuit model was developed to analyze the channel characteristics. A Manchester code was used to increase signal energy. In front of the receiver, an inverter-based amplifier applies to amplify the received data. Then, a Clock and Data Recovery data develops to recover the transmitted data. The chip is fabricated using UMC 0.18um CMOS process with a chip area of 0.75 X 0.7 mm(2), power consumption of 22uW and a data transmission rate of 10M bit per second.
A 48.6-to-105.2 mu W Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications
(2014-04-01)
Hsu, Shu-Yu
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Ho, Yingchieh
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Chang, Po-Yao
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Su, Chauchin
;
Lee, Chen-Yi
A machine- learning ( ML) assisted cardiac sensor SoC ( CS- SoC) is designed for mobile healthcare applications. The heterogeneous architecture realizes the cardiac signal acquisition, filtering with versatile feature extractions and classifications, and enables the higher order analysis over traditional DSPs. Besides, the asynchronous architecture with dynamic standby controller further suppresses the system active duty and the leakage power dissipation. The proposed chip is fabricated in a 90- nm standard CMOS technology and operates at 0.5 V- 1.0 V ( 0.7 V- 1.0 V for SRAM and I/ O interface). Examined with healthcare monitoring applications, the CS- SoC dissipates 48.6/ 105.2 mu W for real- time syndrome detections of ECG- based arrhythmia/ VCG- based myocardial infarction with 95.8/ 99% detection accuracy, respectively.
A digital BIST methodology for spread spectrum clock generators
(2006)
Chou, Maohsuan
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Hsu, Jenchien
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Su, Chauchin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small.
A digital BIST methodology for spread spectrum clock generators0
(2006)
Chou, Maohsuan
;
Hsu, Jenchien
;
Su, Chauchin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small.
A Near-Threshold 480 MHz 78 mu W All-Digital PLL With a Bootstrapped DCO
(2013-11-01)
Ho, Yingchieh
;
Yang, Yu-Sheng
;
Chang, ChiaChi
;
Su, Chauchin
;
交大名義發表
This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm(2). The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 mu W. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 mu W (2.4 mu W) under a supply voltage of 0.5 V (0.25 V).
A test and diagnosis methodology for RF transceivers
(2007)
Chen, Hung-kai
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Su, Chauchin
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper proposes an RF test and diagnosis methodology based on digital DFT structure and built-in DSP function of a SoC Chip. Constellation variation plots are proposed to identify the faulty component. Furthermore, linear interpolation is used to determine the amount of variation. The simulated test results show that the method is able to identify not only the faulty component but also the variation amount precise.
A Tree-Topology Multiplexer for Multiphase Clock System
(2009-01-01)
Lu, Hungwen
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show g that the proposed design can achieve higher bandwidth and be less ss sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mu m CMOS technology. Measured results indicate that the proposed design can operate tip to 7 gigabits/s under 0.3-Ul jitter limitation.
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus
(2009-02-01)
Li, Katherine Shu-Min
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Lee, Chung-Len
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Su, Chauchin
;
Chen, Jwu E.
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電子工程學系及電子研究所
For very deep sub-micrometer VLSI, crosstalk becomes an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.
Adaptive Two-Stage Fuzzy Temperature Control for an Electroheat System
(2009-03-01)
Wang, Chih-Hu
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Lin, Chun-Hung
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Lee, Bore-Kuen
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Liu, Chien-Nan Jimmy
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Su, Chauchin
In this paper, we construct a simple adaptive two-stage fuzzy temperature tracking controller for a commercial electroheat system. Being not well isolated from the environment, it is hard to build an analytical model for the system due to heat convection caused by a fan for heat mixing in the chamber, heat leakage to the environment, variation of the environment temperature, and uncertain nonlinear heating dynamics. Also, as a commercial product by using cheap heater coils and without equipping a cooling system, this system usually has a bad transient response such as a long rise time, a large overshoot, and a long settling time. Moreover, temperature tracking at the steady-state phase is not easy to maintain due to heat interaction with the environment. Here, in the presence of the unknown system dynamics, we use a two-stage fuzzy controller to improve the transient response. Furthermore, a simple fine-tuning adaptive control scheme is proposed to overcome environmental influence and ensure tracking of the temperature setting. Simulation study and experimental results show good performance of the adaptive fuzzy temperature control system.
Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System
(2009-11-01)
Tseng, Yuhwai
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
;
Institute of Electrical and Control Engineering
This study develops a form of digital baseband Intra-Body communication for wideband transmission. A simplified circuit model of signal and noise is constructed to analyze the contribution of the high pass filter function of the electrostatic coupling Intra-Body communication system to wideband digital transmission in electrostatic coupling Intra-Body communication. A unit step function is presented to determine the maximum high pass 3 dB pole that can ensure favorable signal quality in a baseband Intra-Body communication system. Body noise is measured to estimate the range of the high pass 3dB pole with good Signal to Noise Ratio. A 3.3 Volt battery-powered FPGA is experimentally implemented to confirm the feasibility of the wideband Intra-Body communication system. The experimental results indicate that the digital baseband Intra-Body communication system supports a data rate of more than 16MPS.
BIST for measuring clock jitter of charge-pump phase-locked loops
(2008-02-01)
Hsu, Jen-Chien
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Su, Chauchin
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%.
Built-in jitter measurement methodology for spread-spectrum clock generators
(2008)
Hsu, Jenchien
;
Chou, Maohsuan
;
Su, Chauchin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
In this paper, a built-in-self-test methodology for measuring frequency deviation and jitter of spread-spectrum clock generators is presented. It utilizes a phase detector to detect the clock phase of spread spectrum clock (SSC) and then measure the jitter by filtering out the low frequency component of the clock phase. Frequency of spread-spectrum clock can also be obtained by filtering out the high frequency component of the signal. The methodology is analyzed and verified with chip implementation and measurement. As an all digital design, the hardware overhead is very low.
Cumulative Differential Non linearity Testing of ADCs
(2012-10-01)
Chen, Hungkai
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Ho, Yingchieh
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Su, Chauchin
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper proposes a cumulative DNL (CDNL) test methodology for the BIST of ADCs. It analyzes the histogram of the DNL of a predetermined k LSBs distance to determine the DNL and gain error. The advantage of this method over others is that the numbers of required code bins and required samples are significantly reduced. The simulation and measurements of a 12-bit ADC show that the proposed CDNL has an error of less than 5% with only 2(12) samples, which can only be achieved with 2(22) samples using the conventional method. It only needs 16 registers to store code bins in this experiment.
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
(2012-01-01)
Ho, Yingchieh
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Chang, Chiachi
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Su, Chauchin
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電機工程學系
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電控工程研究所
This brief presents a bootstrapped CMOS inverter operated with a subthreshold power supply. In addition to improving the driving ability, a large gate voltage swing from - V-DD to 2V(DD) suppresses the subthreshold leakage current. As compared with other reported works, the proposed bootstrapped inverter uses fewer transistors operated in the subthreshold region. Therefore, our design has shorter delay time. The Monte Carlo analysis results indicate that a sigma of delay time is only 6.3 ns under the process and temperature variations with 200-mV operation. Additionally, a test chip is fabricated in the 90-nm SPRVT low-K CMOS process. Chip measurement results demonstrate the feasibility of operating ten-stage bootstrapped inverters with a 200-fF loading of each stage at 200-mV V-DD. The test chip is able to achieve 10-MHz clock rate at 200 mV V-DD, the power consumption is 1.01 mu W, and the leakage power is 107 nW.
Design of an All-Digital LVDS Driver
(2009-08-01)
Lu, Hungwen
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Wang, Hsin-Wen
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-mu m 1P6M CMOS process with a core area of 0.072 mm(2). At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/bit.
Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers
(2012-06-01)
Ho, Yingchieh
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Chen, Hung-Kai
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Su, Chauchin
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電機工程學系
;
電控工程研究所
This paper investigates the performance of the interconnects with repeater insertion in the subthreshold region. A 3X complementary metal-oxide-semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. In addition, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration under the process and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for 10-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS process. The measured results show that the 3X (4X) predrivers can achieve 5 Mb/s (1.5 Mb/s) data rate at 0.15 V with an efficiency of 35.2 fJ (32.8 fJ).
Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers
(2012-06-01)
Ho, Yingchieh
;
Chen, Hung-Kai
;
Su, Chauchin
;
電子工程學系及電子研究所
;
電控工程研究所
This paper investigates the performance of the interconnects with repeater insertion in the subthreshold region. A 3X complementary metal-oxide-semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. In addition, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration under the process and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for 10-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS process. The measured results show that the 3X (4X) predrivers can achieve 5 Mb/s (1.5 Mb/s) data rate at 0.15 V with an efficiency of 35.2 fJ (32.8 fJ).
Evaluation and Verification of Channel Transmission Characteristics of Human Body for Optimizing Data Transmission Rate in Electrostatic-Coupling Intra Body Communication System: A Comparative Analysis
(2016-02-11)
Tseng, Yuhwai
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Su, Chauchin
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Ho, Yingchieh
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電控工程研究所
;
Institute of Electrical and Control Engineering
Background Intra-body communication is a new wireless scheme for transmitting signals through the human body. Understanding the transmission characteristics of the human body is therefore becoming increasingly important. Electrostatic-coupling intra-body communication system in a ground-free situation that integrate electronic products that are discretely located on individuals, such as mobile phones, PDAs, wearable computers, and biomedical sensors, are of particular interest. Materials and Methods The human body is modeled as a simplified Resistor-Capacitor network. A virtual ground between the transmitter and receiver in the system is represented by a resister-capacitor network. Value of its resistance and capacitance are determined from a system perspective. The system is characterized by using a mathematical unit step function in digital baseband transmission scheme with and without Manchester code. As a result, the signal-to-noise and to-intersymbol-interference ratios are improved by manipulating the load resistor. The data transmission rate of the system is optimized. A battery-powered transmitter and receiver are developed to validate the proposal. Results A ground-free system fade signal energy especially for a low-frequency signal limited system transmission rate. The system transmission rate is maximized by simply manipulating the load resistor. Experimental results demonstrate that for a load resistance of 10k-50k Omega, the high-pass 3 dB frequency of the band-pass channel is 400kHz-2MHz in the worst-case scenario. The system allows a Manchester-coded baseband signal to be transmitted at speeds of up to 20M bit per second with signal-to-noise and signal-to-intersymbol-interference ratio of more than 10 dB. Conclusion The human body can function as a high speed transmission medium with a data transmission rate of 20Mbps in an electrostatic-coupling intra-body communication system. Therefore, a wideband signal can be transmitted directly through the human body with a good signal-to-noise quality of 10 dB if the high-pass 3 dB frequency is suitably selected.