Browsing by Author "Tsai, Hui-Wen"

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Active Guard Ring to Improve Latch-Up Immunity
(2014-12-01)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new design concept named as active guard ring and related circuit implementation to improve the latch-up immunity of ICs are proposed. Using additional sensing circuit and active buffer to turn ON the electrostatic discharge (ESD) protection transistors, the large-dimensional ESD (or I/O) devices can provide or receive extra compensation current to the negative or positive current perturbation during the latch-up current test. The new proposed solution has been verified in 0.6-mu m 5 V process to have much higher latch-up resistance compared with the conventional prevention method of guard ring in CMOS technology.
Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits
(2013-01-01)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
Liu, Yi-Sheng
;
Chuang, Ming-Nan
;
電子工程學系及電子研究所
Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.
Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits
(2013)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
Liu, Yi-Sheng
;
Chuang, Ming-Nan
;
電子工程學系及電子研究所
Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.
Compensation Circuit with Additional Junction Sensor to Enhance Latchup Immunity for CMOS Integrated Circuits
(2015)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A circuit solution to generate compensation current that can decrease the perturbation induced by the external latchup trigger was proposed. The robustness against latchup can be improved by supporting compensation current at the pad under latch-up current test. By inserting additional junctions to sense the latchup trigger current, the injected latchup trigger current can be detected, and then the I/O or ESD-protection devices are used to generate the compensation current that decrease the perturbation to the internal circuits. The proposed design has been successfully verified in a 0.5-mu m BCD process to improve latchup immunity.
Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation
(2007)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
A new 2xVDD-tolerant I/O buffer circuit, realized with only 1xVDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by the experimental results with a signal speed of up to 133 MHz for PCI-X application.
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation
(2010-01-01)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-mu m CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCl-X compatible applications. (C) 2009 Elsevier Ltd. All rights reserved.
Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process
(2011-05-01)
Weng, Yi-Hsin
;
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products. (C) 2011 Elsevier Ltd. All rights reserved.
Improve Latch-up Immunity by Circuit Solution
(2015)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively reduce the latchup trigger current that injecting into the core circuit blocks. Therefore, the latchup immunity of I-test with positive or negative trigger current applied at the I/O pins can be significantly improved.
Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers
(2015-06-01)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The robustness against latch-up in the integrated circuits can be improved by supporting complementary current at the pad under the latch-up current test (I-test). By inserting additional junctions to form parasitic bipolar sensors, the external trigger can be monitored, and the ESD protection devices can be applied to provide such current and decrease the related perturbation to the internal circuits. The proposed design and the previous work with a single guard ring have been fabricated in the same 0.5-mu m 5-V process. The experimental results confirm the enhanced latch-up tolerance of this work and the practicability in the SOC era.
Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits
(2014-03-01)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presented a practical industry case of electrical overstress (EOS) failure induced by the latchup test in high-voltage integrated circuits (ICs). By using proper layout modification and additional circuit, the unexpected EOS failure, which is caused by negative-current-triggered latchup test, can be successfully solved. The new design with proposed solutions has been verified in the 0.6-mu m 40-V Bipolar CMOS DMOS (BCD) process to pass the test for at least 500-mA trigger current, which shows high negative-current-latch-up immunity without overstress damage, compared with the protection of only the guard ring. Such solutions can be adopted to implement high-voltage-applicable IC product to meet the industry requirement for the mass production of IC manufactures and applications.