Browsing by Author "Tsou, Wen-An"
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Item type:Item, A CMOS distributed amplifier with current reuse optimization(2006) ;Chou, Mei-Fen ;Tsou, Wen-An ;Dunn, Robert H. ;Huang, Hsiang-LinWen, Kuei-AnnA CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption while retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only,12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-mu m CMOS technology. An analog behavior model is also developed for system-level simulation to shorten the design time and increase design quality for future integrated wide.-band transceivers.Item type:Item, A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with V(dd)/AM and V(dd)/PM Compensations in EER System(2009) ;Tsou, Wen-An ;Wuen, Wen-Shen ;Wen, Kuei-Ann ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsAn auto-biasing cascode class-E PA which can compensate the V(dd)/AM and V(dd)/PM distortion resulting from supply modulation has been proposed. The output voltage of auto-biasing control circuit is generated and varied linearly with PA's supply voltage so that the cascode transistor is degenerated into a resistance and the PA's nonlinear distortion can be compensated. The simulation result shows that the distortion is compensated evidently and the system co-simulation demonstrated that system EVM can be improved from -17 to -19dB. Also, the drain efficiency of the PA can be improved 15% within small supply voltage range.Item type:Item, A Design of CMOS Class-E Power Amplifier with Phase Correction for Envelope Elimination and Restoration (EER)/Polar Systems(2010-01-01) ;Tsou, Wen-An ;Wuen, Wen-Shen ;Wen, Kuei-Ann ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsA circuit technique to correct V(dd)/PM distortion and improve efficiency as supply modulation of cascode class-E PAs has been proposed. The experimental result shows that the phase distortion can be improved from 20 degrees to 5 degrees. Moreover, a system co-simulation result demonstrated that the EVM can be improved from -17 dB to -19 dB.Item type:Item, A Polar Modulated CMOS Class-E Amplifier with a Class-F Driver Stage(2009) ;Tsou, Wen-An ;Wuen, Wen-Shen ;Wen, Kuei-Ann ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsThis work presents a fully integrated polar modulated CMOS class-E amplifier in a 0.18 mu m CMOS process. The amplifier using the device-stacking topology is implemented with a self-biased control circuit, which allows the stacked device operating as a resistance, for linearizing the AM-AM and AM-PM distortion. The simulation result shows that the AM-PM distortion is reduced from 18 degrees to 3 degrees. The linearized class-E amplifier with the class-F driver stage can provide the maximum power gain of 21 dB, the maximum output power of 17 dBm, and the peak power-added efficiency (PAE) of 30% from the supply voltage of 2 V.Item type:Item, A Polar Modulated Tri-band Power Amplifier Using Flexible Substrate Based MEMS Switches(2010-01-01) ;Lai, Chung-Min ;Chao, Tzu-Yuan ;Tsou, Wen-An ;Chou, Mei-FenCheng, Yu-TingIn this work, the phase compensation techniques by means of self-biasing control and an additional tuning capacitor for polar modulated tri-band Class-E power amplifier is proposed. The tri-band power amplifier operating at 2.3 similar to 2.7/3.3 similar to 3.8/5.1 similar to 5.8 GHz for WLAN and WiMAX applications adjusts low loss Micro-Electro-Mechanical-Systems (MEMS) switches to select the matching networks. The improvement of phase distortion and system relative constellation error (RCE) is 36.4 degrees and 8.9dB, respectively. Simulation results shows that the maximum power-added efficiency (PAE) of 34.9%, drain efficiency of 37.3%, and output power of 18.8dBm from 2.8V supply can be achieved in 0.18 mu m CMOS Technology.Item type:Item, An energy saving scheme for long range and high data rate wireless sensor networks(2007) ;Lin, Li-Hsieh ;Tsou, Wen-An ;Fan, Long-Sheng ;Wuen, Wen-ShenWen, Kuei-AnnFor increasing demands on transceiving coverage, reliability and high resolution of sensing data in modem wireless sensor network applications, a novel digital transceiver scheme for wireless sensor node with integration of WiMAX PHY QoS, and low-density parity check (LDPC) code had been proposed. It will be 67% energy saving to support high gain sensing amplifier thus to provide high resolution digitization of sensing data. With WiMAX based regulation, 30 mile transmission range and 74Mbps data rate for long range and high data rate wireless sensor networks can be achieved.Item type:Item, Analysis for Efficiency Improvement of CMOS Class-E Power Amplifiers with MEMS Inductors(2009) ;Tsou, Wen-An ;Chen, Che-Sheng ;Wang, Chun-Kai ;Chen, Kevin C. J.Wu, Svu-HsienThis paper presents an analysis and enhancement of efficiency in a class-E power amplifier using MEMS inductors. The M EMS technology is proposed and demonstrated by a prototype inductor. The model of MEMS inductors is created by HFSS simulator and its simulated result has good match with the measured result. Stacked-metal layer inductors in MEMS process are also developed to increase the quality factor. The simulation result of a CMOS class-E PA with MEMS inductors shows that the increased quality factor of inductors by 2 can improve the PA's efficiency by 6%. Furthermore, we present a design methodology for optimizing the PA's efficiency.Item type:Item, TRI-BAND CMOS CLASS-E POWER AMPLIFIER DESIGN WITH PHASE COMPENSATIONS FOR POLAR SYSTEMS(2010) ;Lai, Chung-Min ;Tsou, Wen-An ;Chou, Mei-Fen ;Wen, Kuei-Ann電子工程學系及電子研究所A 0.18 mu m CMOS fully integrated cascode Class-E power amplifier operating in 2.5GHz/3.5GHz/5.2GHz frequency bands for polar transmitters has been proposed. The tri-band amplification is achieved by adaptation of the common-gate transistor size and the matching networks. The phase distortion from supply modulation of the Class-E is compensated by controlling the common-gate transistor gate voltage and a compensative capacitor. Simulation results show that the maximum power-added efficiency (PAE) of 30.4%, drain efficiency of 34% and output power of 18.8dBm from 2.8V supply can be achieved. The phase distortion can be compensated from 34.4 degrees to 3.1 degrees under supply voltage of 0.5V to 2.8V. A system co-simulation has been established for relative constellation error (RCE) evaluation and it reveals that the RCE can be improved from -23.3dB to -31.4dB in 3.5GHz frequency band.