Browsing by Author "Tu, Ming-Hsien"

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28nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
(2016)
Hsu, Wei-Shen
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chuang, Ching-Te
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Hwang, Wei
In this paper, an ultra-low-power near-/sub-threshold first-in-firstout (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512x16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
(2014-09-01)
Chiu, Yi-Wei
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Hu, Yu-Hao
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Tu, Ming-Hsien
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Zhao, Jun-Kai
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Chu, Yuan-Hua
This paper presents a new bit-interleaving 12T sub-threshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical V-DD to 350 mV (similar to 100 mV lower than the threshold voltage) with V-DDMIN limited by Read operation. Data can be written successfully for V-DD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 mu W at 350 mV, 25 degrees C.
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
(2015-05-01)
Lu, Chien-Yu
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Chuang, Ching-Te
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Jou, Shyh-Jye
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Tu, Ming-Hsien
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Wu, Ya-Ping
This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V-DD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 degrees C. At 0.325 V and 25 degrees C, the chip operates at 600 kHz with 5.78 mu W total power and 4.69 mu W leakage power, offering 2x frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 degrees C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
(2012-12-01)
Lu, Chien-Yu
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Tu, Ming-Hsien
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Yang, Hao-I
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Wu, Ya-Ping
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Huang, Huan-Shun
This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 x 385 mu m(2) 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 degrees C. The measured total power consumption is 3.94 mu W at 0.33 V, 500 kHz, and 25 degrees C.
A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
(2016-05)
Wu, Shang-Lin
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Lu, Chien-Yu
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Tu, Ming-Hsien
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Huang, Huan-Shun
;
Lee, Kuen-Di
This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tristate pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128 kb SRAM macro implemented in 40 nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with V-DD down to 0.35 V (similar to 100 mV lower than the threshold voltage). Data is held down to 0.325 V with 2.53 mu W standby power. The measured maximum operation frequency is 375 kHz with total power consumption 5.43 mu W at 0.35 V. (C) 2016 Elsevier Ltd. All rights reserved.
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
(2017-07-01)
Wu, Shang-Lin
;
Li, Kuang-Yu
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Huang, Po-Tsang
;
Hwang, Wei
;
Tu, Ming-Hsien
This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron).
A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist
(2013)
Chiu, Yi-Wei
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Hu, Yu-Hao
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Tu, Ming-Hsien
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Zhao, Jun-Kai
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Jou, Shyh-Jye
This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for V-DD down to 0.32 V (similar to 0.69X of threshold voltage) with V-DDMIN limited by Read operation. The measured maximum operation frequency is 3.5 MHz (16.5 MHz) at 0.32 V (0.38 V) with total power consumption of 15.2 mu W (27.2 mu W) at 25 degrees C.
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
(2014-12-01)
Lien, Nan-Chun
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Chu, Li-Wei
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Chen, Chien-Hen
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Yang, Hao-I.
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Tu, Ming-Hsien
This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%-44% read access performance improvement and 2x-3.5x variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V.
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
(2013-01-01)
Liao, Wei-Nan
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Lien, Nan-Chun
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Chang, Chi-Shin
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Chu, Li-Wei
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Yang, Hao-I
This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive DataAware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 1.07GHz@1.2V and 887MHz@1.1V at 25 degrees C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25 degrees C.
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
(2013)
Chang, Chi-Shin
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Yang, Hao-I
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Liao, Wei-Nan
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Lin, Yi-Wei
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Lien, Nan-Chun
We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25 degrees C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25 degrees C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25 degrees C.
A reconfigurable MAC architecture implemented with mixed-V(t) standard cell library
(2008)
Wang, Li-Rong
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Chiu, Yi-Wei
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Hu, Chia-Lin
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Tu, Ming-Hsien
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Jou, Shyh-Jye
In this paper, a 32-bit reconfigurable multiplication-accumulation architecture, which can execute flexibly one 32x32, two 16x16 or four 8x8 two's complement multiply-accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-V(t) CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design.
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
(2012-06-01)
Tu, Ming-Hsien
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Lin, Jihi-Yu
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Tsai, Ming-Chien
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Lu, Chien-Yu
;
Lin, Yuh-Jiun
This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-inter-leaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V-DD down to 0.35 V (similar to 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 mu W power. Data is held down to 0.275 V with 2.29 mu W Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V-DD around/above 1.0 V.
Asymmetrical Write-Assist for Single-Ended SRAM Operation
(2009)
Lin, Jihi-Yu
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Tu, Ming-Hsien
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Tsai, Ming-Chien
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Jou, Shyh-Jye
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Chuang, Ching-Te
In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a single-ended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, V(min) of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
(2010-12-01)
Tu, Ming-Hsien
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Lin, Jihi-Yu
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Tsai, Ming-Chien
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Jou, Shyh-Jye
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Chuang, Ching-Te
In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V(DD), an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 mu W.
Testing Strategies for a 9T Sub-threshold SRAM
(2012)
Yang, Hao-Yu
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Lin, Chen-Wei
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Chen, Hung-Hsin
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Chao, Mango C. -T.
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Tu, Ming-Hsien
Due to the increasing demands of lower-power devices, a lot of research effort has been devoted to develop new SRAM cell designs that can be effectively and economically operated at the subthreshold region. However, each new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAMs and require specialized test methods to detect those uncovered fault models. In this paper, we focus on developing the test methods for testing a new 9T subthreshold SRAM design, which utilizes single bit-line read/write, two write word-lines for writing different values, and a separate read path. A mixed march algorithm with different background and address-traverse directions is proposed to detect various uncovered fault models and validated through real test chips. A new specialized technique of floating bit-line attacking is also presented to detect the stability faults, which cannot be effectively detected by applying the conventional test methods, for the new 9T SRAM design.
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design
(2011-06-01)
Wang, Li-Rong
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Tu, Ming-Hsien
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Jou, Shyh-Jye
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Lee, Chung-Len
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電機工程學系
This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 32 x 32, two 16 x 16 or four 8 x 8 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-V(t) standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V(t) standard cell library.