Browsing by Author "WU, CY"

Now showing 1 - 20 of 159

A 1.5 V CMOS balanced differential switched-capacitor filter with internal clock boosters
(1995)
WU, CY
;
WEY, WS
;
YU, TC
;
電機學院
;
College of Electrical and Computer Engineering
A 1.5 v CMOS current-mode cyclic analog-to-digital converter with digital error correction
(1995)
CHEN, CC
;
WU, CY
;
CHO, JJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES
(1994-11-01)
CHIN, SY
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-mu m double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources, In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to +/- 1/2 LSB is within 8 ns. The chip area is 1.8 mm x 1.0 mm.
A 2-D ANALYTIC MODEL FOR THE THRESHOLD-VOLTAGE OF FULLY DEPLETED SHORT GATE-LENGTH SI-SOI MESFETS
(1995-12-01)
HOU, CS
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A two zone Green's function solution method is proposed to analytically model the potential distribution in the silicon film of fully depleted SOI MESFET's, in which the exact solution of 2-D Poisson's equation is obtained by using the appropriate boundary conditions, From the derived analytic 2-D potential distribution, the bottom potential in the active silicon film is used to analyze the drain-induced barrier lowering effect and the threshold voltage is defined in terms of minimum channel potential barrier, The results of the developed analytic threshold-voltage model are compared with those of 2-D numerical simulation, and good agreements are obtained for the gate length down to 0.1 mu m with wide ranges of structure parameters and bias conditions.
A 3-V 1-GHz low-noise bandpass amplifier
(1995)
WU, CY
;
HSIAO, SY
;
LIU, RY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A CHARACTERIZATION MODEL FOR CONSTANT CURRENT STRESSED VOLTAGE-TIME CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE
(1986-12-01)
CHEN, CF
;
WU, CY
;
交大名義發表
;
工學院
;
National Chiao Tung University
A CHARACTERIZATION MODEL FOR RAMP-VOLTAGE-STRESSED IV CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE
(1986-10-01)
CHEN, CF
;
WU, CY
;
交大名義發表
;
工學院
;
National Chiao Tung University
A CHARACTERIZATION TECHNIQUE FOR THE DEGRADATION CHARACTERISTICS OF TI/SI SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS AFTER THERMAL SILICIDATION
(1994-02-01)
LOU, YS
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of thermal silicidation on both the nonideal current-voltage characteristics of the Schottky-banier diodes and the degradation properties of the ohmic contacts have been self-consistently characterized by using a simple interfacial-layer theory. The abruptly changed nonideality of the measured I-V characteristics as TiSi2 is formed can be interpreted as the variations of the interface properties, such as the thermal-equlibrium barrier height, the interfacial-layer capacitance, and the density distribution of the interface state. Moreover, different work functions for Ti and TiSi2 and the change of the dominant type of the interface states and their density distributions are shown to be responsible for the fluctuations of the thermal-equilibrium barrier height after thermal silicidation. Furthermore, the interface parameters extracted from the fabricated Schottky-barrier diodes are used to calculate and compare the simultaneously-processed specific contact resistivities, and satisfactory agreement is obtained. Thus, the silicidation-related degradation characteristics of the ohmic contacts can be directly related to the variations of the interface properties at the Ti/Si interface.
A CMOS CURRENT-MODE DESIGN OF MODIFIED LEARNING-VECTOR-QUANTIZATION NEURAL NETWORKS
(1995-09-01)
LIU, RY
;
WU, CY
;
JOU, IC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A modification of LVQ model, Modified LVQ (MLVQ) model, is proposed for the estimation of centroid in pattern recognition. Computer simulation results are presented which demonstrate the behavior of the MLVQ model in estimating the class centroid by utilizing the distance-dependent step size. The results indicate the high potential of less dependence on the initial point as well as the precise settlement of the weight vectors to the centroids. The main feature is that the proposed model is robust to the noise perturbation between two pattern distributions in practical applications. To take advantage of this MLVQ model with the faster training and recalling process for patterns, a hybrid analog-digital processing system is designed by the CMOS current-mode integrated circuit (IC) technology and offers the best attributes of both analog and digital computation. This hybrid processing system operates at microsecond time scale, which enables it to produce real time solutions for complex spatiotemporal problems found in high speed signal processing applications. The overall neural processing system has also been simulated and verified by the HSPICE circuit simulator.
A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES
(1995-05-01)
WU, CY
;
CHEN, CC
;
CHO, JJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Fully-differential current-mode circuit techniques are developed for the design of a pipelined current-mode analog-to-digital converter (IADC) in the standard CMOS digital processes. In the proposed IADC, the 1-b-per-stage architecture based on the reference nonrestoring algorithm is adopted. Thus large component ratios can be avoided and the linearity errors caused by device mismatches can be minimized. As one of the key subcircuits in the IADC, an offset-canceled high speed differential current comparator (CCMP) is proposed and analyzed. In the CCMP, the subtractions of offsets are performed in the current domain without floating capacitors. Moreover, the other key subcircuit, the current sample-and-hold amplifier (CSHA), is also developed to realize the pipeline architecture. An experimental chip for the proposed IADC has been fabricated in 0.8-mu m n-well CMOS technology. Using a single 5-V power supply, the fabricated IADC can be operated at 4,5-Ms/s conversion rate with a signal-to-noise-and-distortion-ratio (SNDR) of 51 dB (effective 8.2-b) for the input signal at 453 kHz. For 8-b resolution, the fabricated IADC can be operated at 4,5-Ms/s conversion rate with both differential nonlinearity (DNL) and integral nonlinearity (INL) below +/-0.6 LSB. The power consumption and the active chip area are 16 mW/b and 0.73 mm(2)/b, respectively.
A COMPUTER-AIDED SIMULATION-MODEL FOR THE IV CHARACTERISTIC OF M-N-P SILICON SCHOTTKY-BARRIER DIODES PRODUCED BY USE OF LOW-ENERGY ARSENIC-ION IMPLANTATION
(1983)
WU, CY
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CHANG, MC
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SHEY, AJ
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交大名義發表
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電子物理學系
A HIGH-DENSITY MOS STATIC RAM CELL USING THE LAMBDA BIPOLAR-TRANSISTOR
(1983)
WU, CY
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LIU, YF
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
A LOW GLITCH 10-BIT 75-MHZ CMOS VIDEO D/A CONVERTER
(1995-01-01)
WU, TY
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JIH, CT
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CHEN, JC
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WU, CY
;
電子工程學系及電子研究所
A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 mu m single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV.s and the settling time within +/- 0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 170 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm x 1.2 mm (1.75 mm x 0.7 mm for the DAC portion).
A NEW 2-DIMENSIONAL MODEL FOR THE POTENTIAL DISTRIBUTION OF SHORT GATE-LENGTH MESFETS AND ITS APPLICATIONS
(1992-08-01)
CHIN, SP
;
WU, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new analytical technique for calculating the two-dimensional (2D) potential distribution of a MESFET device operated in the subthreshold region is proposed, in which the 2D Poisson's equation is solved by the Green's function technique. The potential and electric-field distributions of a non-self-aligned MESFET device are calculated exactly from different types of Green's function in different boundary regions, and the sidewall potential at the interface between these regions can be determined by the continuation of the electric field at the sidewall boundary. The remarkable feature of the proposed method is that the implanted doping profile in the active channel can be treated. Furthermore, a simplified technique is developed to derive a set of quasi-analytical models for the side-wall potential at both sides of the gate edge, the threshold voltage of short gate-length devices, and the drain-induced barrier lowering. Moreover, the developed quasi-analytical models are compared with the results of 2D numerical analysis and good agreements are obtained.
A NEW 2D ANALYTIC THRESHOLD-VOLTAGE MODEL FOR FULLY DEPLETED SHORT-CHANNEL SOI MOSFETS
(1993-09-01)
GUO, JY
;
WU, CY
;
電控工程研究所
;
Institute of Electrical and Control Engineering
The exact solution of the 2D Poisson's equation for the fully depleted SOI MOSFET's is derived by using a three-zone Green's function solution technique. Based on the derived 2D potential distribution, the front and back surface potential distributions in the Si film are analytically obtained and their accuracy are verified by 2D numerical analysis. The calculated minimum surface potential and its location are used to analyze the drain-induced barrier-lowering effect and further to develop an analytic threshold-voltage model. Comparisons between the developed analytic threshold-voltage model and the 2D numerical analysis are made. It is shown that excellent agreements are obtained for wide ranges of device structure parameters and applied biases.
A NEW ALGORITHM FOR STEADY-STATE 2-D NUMERICAL-SIMULATION OF MOSFETS
(1990-02-01)
PERNG, RK
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WU, CY
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交大名義發表
;
工學院
;
National Chiao Tung University
A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES
(1986-04-01)
CHEN, MJ
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WU, CY
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交大名義發表
;
工學院
;
National Chiao Tung University
A NEW APPROACH TO ANALYTICALLY SOLVING THE TWO-DIMENSIONAL POISSON EQUATION AND ITS APPLICATION IN SHORT-CHANNEL MOSFET MODELING
(1987-09-01)
LIN, PS
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WU, CY
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交大名義發表
;
工學院
;
National Chiao Tung University
A NEW APPROACH TO MODEL CMOS LATCHUP
(1985)
WU, CY
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YANG, YH
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CHANG, C
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CHANG, CC
;
工學院
A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
(1995)
WU, CY
;
CHENG, KH
;
LU, JH
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics