Browsing by Author "Wen, KA"

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3DPAC Video Codec Transmission over Internet with QoS Provision
(2000)
Wen, KA
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Chiou, CH
;
Chen, AY
;
Lin, CH
;
Lin, JL
In this work, a VOD-like network application especially for wireless LAN and low bit rate Internet transmission. With the derivation of the software platform, Three-dimensional Polynomial Approximation Coding (3DPAC) video compression algorithm is employed and some TCP/IP network operation is driven. A simple experimental video transmission platform over TCP/IP is constructed to investigate the features for guarantee of quality of service development of this video compression and transmission system, and two excellent features, fidelity and agility of 3DPAC for QoS development are discovered.
A CMOS low-noise amplifier for ultra wideband wireless applications
(2005-11-01)
Chou, MF
;
Wuen, WS
;
Wu, CC
;
Wen, KA
;
Chang, CY
A CMOS low noise amplifier (LNA) for low-power ultrawideband (UWB) wireless applications is presented. To achieve low power consumption and wide operating bandwidth, the proposed LNA employing stagger tuning technique consists of two stacked common-source stages with different resonant frequencies. This work is implemented in 0.18-mu m CMOS process and shows a 2.4-9.4-GHz bandwidth. The amplifier provides a maximum forward gain (S-21) of 10.9 dB while drawing 7.1 mW from a 1.8-V supply. A noise figure as low as 4.1 dB and an IIP3 of -3.5 dBm have been demonstrated.
A dual-band switchable 5-GHz CMOS low noise amplifier for wireless multimedia applications
(2003-06-01)
Wuen, WS
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The paper presents a dual-band switchable low noise amplifier implemented in 0.25-mum CMOS technology for 5GHz wireless multimedia applications. The high-speed wireless multimedia applications call for broadband design techniques for RF circuits. Instead of using conventional broadband techniques not well suitable for CMOS implementation, a dual-band switchable load is proposed for broadband LNA design. The dual-band switchable load enables the LNA operate at the lower or the upper band at 5-GHz band by a 1-bit control signal. The LNA exhibits over 17 dB power gain, 3.5 dB noise figure and input 1-dB compression point -23dBm in both frequency bands. It draws 9.5 mA from 2.5 V supply. The power gain remains larger than 16 dB as temperature varies from -5 to 65degreesC.
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique
(2006-02-01)
Chang, MF
;
Chiou, LY
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Crosstalk between bitlines induces read failure and limits the coverage of applicable code-patterns for high-speed contact/via-programming read-only memories (ROMs) in SoC. Owing to the variation in bitline loading across code-patterns, the amount of coupled noise on an accessed bitline is code-pattern-dependent. This crosstalk effect worsens, with larger coupling capacitance and smaller intrinsic loading, as the technology node shrinks. This study proposes dynamic virtual guardian (DVG) techniques for contact/via-programming ROM macros and compilers to eliminate the crosstalk-induced read failure and increase the code-patterns coverage. Compared with conventional ROMs, DVG techniques achieve higher speed, lower power consumption and better design for manufacturing (DFM) capability with full code-patterns coverage. Experiments on fabricated designs, a conventional ROM and two 256 Kb DVG ROMs, using 0.18 mu m 1P5M CMOS technology have demonstrated that DVG techniques achieve 100% code-pattern coverage under a small sensing margin.
A low noise CMOS current folded mixer for direct conversion receivers
(2004-06-01)
Wuen, WS
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A current folded mixer achieving low l/f noise for low power direct conversion receivers is proposed. The proposed mixer topology decouples the design tradeoffs between noise figure, conversion gain and third order intermodulation distortion. Comparisons with the conventional current-reuse injection topology, the current folded mixer with l/f noise minimized shows significant improvements. Experimental design on 2.4-GHz band and with 0.18-mum CMOS technology has revealed the advantages of the newly proposed topology.
A low power CMOS low noise amplifier for ultra-wideband wireless applications
(2005)
Wu, CC
;
Chou, MF
;
Wuen, WS
;
Wen, KA
;
電子工程學系及電子研究所
A CMOS low noise amplifier (LNA) for low-power ultra-wideband (UNVB) wireless applications is presented. To achieve low power consumption and wide operating bandwidth, the proposed LNA employing stagger tuning technique consists of two stacked common-source stages with different resonance frequencies. This work is implemented in 0.18-mu m CMOS process and shows a 2.6-9.2-GRz bandwidth. The amplifier provides a maximum forward gain (S(21)) of 10.9 dB while drawing 7.1 mW from a 1.8-V supply. A noise figure as low as 3.5 dB and an IIP3 of -5.1 dBm have been demonstrated. In this paper, design optimization for the power-constrained stacked amplifiers in wide bandwidth applications is also presented.
A low-complexity 3-stage parallel interference cancellation receiver (LCPIC) for DS-CDMA cellular systems
(2001)
Huang, CW
;
Wen, KA
;
電機學院
;
College of Electrical and Computer Engineering
A low complexity 3-stage parallel interference cancellation (LCPIC) receiver for DS-CDMA cellular systems is proposed and analyzed in this work. Based on numerical analyses, the power efficiency of the LCPIC receiver is close to that of the 3-stage PIC receiver and better than that of the 2-stage PIC receiver in AWGN with either perfect power control or log-normal power control error. In addition, the near-far resistance of the LCPIC, 2-stage, 3-stage PIC, and SIC receivers are analogous since their performance are undistinguishable in near-far channels. Still more, the computational complexity, which is In terms of the needs of flops per bit decision, of the LCPIC receiver is much less than that of the 3-stage PIC receiver and only a little more than that of the 2-stage PIC receiver.
A macro model of silicon spiral inductor
(2002-05-01)
Su, CY
;
Chen, LP
;
Chang, SJ
;
Tseng, BM
;
Lin, DC
A new automatic parameter extraction method for modeling Of silicon Spiral inductors is presented. The Concepts on self-resonance frequency (f(sr)) and quality factor of a spiral inductor are utilized to develop the concise extraction procedures. In the mean time, the presented extraction procedures are programmed as a macro to execute all the extractions automatically and shorten the extraction time effectively. Without any additional optimization or curve fitting, almost all the patterns of S-parameters between the measured and the simulation of extracted data implemented with the extraction macro are less than 5%. The programmed extraction macro makes it fast and accurate to extract and characterize the behaviours or silicon-based spiral inductors with different structures and substrate resistivities. It provides a concrete foundation commercial silicon radiofrequency (RF) Circuit design to realizing on-chip silicon RF integrated circuits. Furthermore, the directly extracted equivalent model parameters, without an optimization, also provide a rule to fairly, effectively and phsically judge the performance of a spiral inductor. (C) 2002 Elsevier Science Ltd. All rights reserved.
A programmable pipelined digital differential matched filter for DSSS receiver
(2001-11-01)
Chiou, CH
;
Huang, CW
;
Wen, KA
;
Wu, ML
;
電子工程學系及電子研究所
A programmable pipelined digital differential matched filter (PDMF) implemented for a direct sequence spread spectrum receiver is proposed in this paper. To reduce the power consumption, the architecture PDMF is based on the synchronization combined PN code phase acquisition algorithm (Huang et al., 1999). Compared with the conventional PN code phase acquisition algorithm, the theoretical analysis result indicates that the PDMF acquires both power efficient and preferable detection. Depending on different applications, programmability allows the PDMF to implement 3-tap, 5-tap, or 11-tap Barker codes with the same hardware but different precisions for each tap coefficient. For short tap Baker codes, the architecture could adopt more precision on each tap coefficient to resist the channel noise. Simulation results also show that there are fewer errors of high sample precision with the same tape.
A systematic design of protocol processors
(1996)
Chen, AY
;
Chen, YS
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Chang, RC
;
Wen, KA
;
交大名義發表
An innovative design methodology is proposed for protocol processors design. The protocol description is mapped to statecharts and statecharts are then mapped to a real-time operating system as well as microprocessors. The IS-54 protocol for cellular wireless communication mobile station is taken as the design example. And an efficient and easy-for-evaluation design environment is then constructed.
An automatic macro program for radio frequency MOSFET characteristics analysis
(2001-10-01)
Su, CY
;
Chang, SJ
;
Chen, LP
;
Ho, YP
;
Huang, GW
The parameter extraction language (PEL) in Agilent IC-CAP software is used to develop an automatic macro program for the analysis of the characteristics of RF MOSFETs. By using this powerful macro program, the time spent on the measurement of the MOSFET characteristics and the related analysis is effectively reduced. This macro program permits a fast and accurate method to obtain the DC and RF characteristics of MOSFETs with different device geometries and operating conditions. It is also suitable for high volume measurements and analyses of MOSFET, and provides a solid jou 71 dation for RF circuit design.
CMOS RFIC: Application to wireless transceiver design
(2000-02-01)
Wen, KA
;
Wuen, WS
;
Huang, GW
;
Chen, LP
;
Chen, KY
There is increasing interest using CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper reviews recent works in transceiver architectures, circuits and devices technology for CMOS RFIC application. A number of practical problems those must be resolved in CMOS RFIC design are also discussed.
Code-pattern insensitive embedded ROMs using dynamic bitline shielding technique
(2005-07-21)
Chang, MF
;
Chiou, LY
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A dynamic bitline shielding (DBS) technique is proposed for highspeed via-programming ROMs, to eliminate code-pattem-dependent crosstalk-induced read failure (CIRF) and increase code-pattem coverage. Fabricated 256 Kb conventional and DBS ROMs demonstrated that the DBS technique can eliminate the CIRF and operate with a small sensing margin.
CORDIC-based architecture with channel state information for OFDM baseband receiver
(2005-05-01)
Peng, CS
;
Chuang, YS
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An efficient architecture for OFDM baseband receiver based on coordinate rotation digital computer (CORDIC) algorithm is proposed with channel state information (CSI). Two dual-mode CORDIC modules are designed for synchronization and equalization. A modified demapping method using CSI helps to provide sub-channel status, and therefore decreases packet error rates especially for some sub-channels with extremely low SNR. A combined algorithm suitable for CORDIC is proposed for not only estimate and compensation of channels but synchronization for carrier frequency offset and sampling. clock offset. Allocation, timing analysis and complexity for all functional blocks in the receiver are proposed, including front-end processing, FFT inner receiver, and outer receiver. Complete tests for packet error rate are simulated under an integrated platform considering of RF front-end non-ideal parameters, filters, quantization, and channel models. Simulation results Of practical circuits on AWGN and channel models are presented and prove the improvement of the receiver. The design occupies about 424k equivalent gate count and 7.3 mm(2) core size in 0.18 mu m CMOS.
Crosstalk-insensitive via-programming ROMs using content-aware design framework
(2006-06-01)
Chang, MF
;
Chiou, LY
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Various code patterns of a via-programming read only memory (ROM) cause significant fluctuations in coupling noise between, bitlines (BLs). This crosstalk between BLs leads to read failure in high-speed via-programmable ROMs and limits the coverage of applicable code patterns. This work presents a content-aware design framework (CADF) for via-programming ROMs to overcome the crosstalk induced read failure. The CADF ROMs employ a content-aware structure and correspondent code-structure programming algorithm to reduce the amount of coupling noise source while maintaining nonminimal BL load for crosstalk reduction. A 256-Kb conventional ROM and a 256-Kb CADF ROM were fabricated using a 0.25-mu m logic CMOS process. The measured results ascertain that the read induced read failure is suppressed significantly by CADF. The CADF ROM also reduced 86.2% and 94.5% in power consumption and standby current compared to the conventional ROM, respectively.
Dual-band mixer design
(2005-06-01)
Chou, MF
;
Wen, KA
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a dual-band mixer equipped with a dual-band load using current combine technique to minimize chip area by sharing inductors for each frequency band. A systematic design methodology for the current combine load based on parasitic effect considerations is also developed. By following the proposed design procedure, the load inductance and combine capacitance for the dual-band mixer can be easily determined. A 2.4/5.2-GHz CMOS mixer design has been implemented to demonstrate the feasibility of the design technique.
Dual-band switchable low noise amplifier for 5-GHz wireless LAN radio receivers
(2002)
Wuen, WS
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The paper presents a dual-band switchable low noise amplifier implemented in 0.25-mum CMOS technology for 5-GHz wireless local area network (WLAN) applications. Equipped with a PMOS capacitor together with the inductive load, the LNA is able to operate at the lower or the upper band at 5-GHz by 1-bit control signal. The LNA exhibits over 17 dB power gain, 3.5 dB noise figure and input 1-dB compression point -23 dBm in both frequency bands. The LNA draws 9.5 mA from 2.5 V supply.
Dual-mode Viterbi decoder design for cellular mobile
(1996)
Chen, AY
;
Wu, CY
;
Wen, KA
;
交大名義發表
;
電子工程學系及電子研究所
The Viterbi algorithm is widely applied for communication to derive the maximun-likehood sequence estimates of transmitted data on channels with intersymbol interference (ISI) and/or coding. In this paper, we provide a VLSI design of Viterbi decoder for IS-54. Design features includes: switchable (2,1,5),(4,1,5) coder design, data inter-leaving, soft - decision. For hardware constrain, area efficiency is of great concern in handset design. Hence, optimized area efficient design is imple-mented.
Early-late gate receiving for Bluetooth packet
(2001)
Peng, CS
;
Chang, MH
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analog-to-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.
Effect of coplanar probe pad design on noise figures of 0.35 mu m MOSFETs
(2000-07-20)
Su, CY
;
Chen, LP
;
Chang, SJ
;
Huang, GW
;
Ho, YP
The effects of different coplanar ground-signal-ground (GSG) probe pads on the noise figure characteristics of submicron MOSFETs are presented. Devices with top-level metal as probe pads shielded by grounded bottom-level metal possess the most appropriate probe pad structure for characterising the noise performance of MOSFETs. Equivalent circuits of the probe pads are used to explain the different noise behaviours.