Browsing by Author "Wen, Kuei-Ann"

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A 2.5GHz 90nm CMOS triple gain mode LNA for WiMAX applications
(2007-01-01)
Chen, Che-Sheng
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Wuen, Wen-Shen
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Wen, Kuei-Ann
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a 2.5GHz 90nm CMOS triple gain mode LNA for WiMAX standard. Because of the high linearity and wide dynamic range requirement in WiMAX applications, the LNA provides triple gain mode for different receiving conditions. The LNA allows to be switched among high gain mode, E W sinking mode, and high linear mode. Without introducing additional inductors in three gain modes, this work is suitable for system integration. The simulation result shows 1.8 dB noise figure can be achieved at high gain mode for small input signal levels. With IMD sinking technique, the input-referred IP3 is about 7.5 dBm for large interferences. For larger input signal levels, the input P1dB at high linear mode is -2.3 dBm.
A 2.5GHz 90nm CMOS triple gain mode LNA for WiMAX applications
(2007-01-01)
Chen, Che-Sheng
;
Wuen, Wen-Shen
;
Wen, Kuei-Ann
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a 2.5GHz 90nm CMOS triple gain mode LNA for WiMAX standard. Because of the high linearity and wide dynamic range requirement in WiMAX applications, the LNA provides triple gain mode for different receiving conditions. The LNA allows to be switched among high gain mode, E W sinking mode, and high linear mode. Without introducing additional inductors in three gain modes, this work is suitable for system integration. The simulation result shows 1.8 dB noise figure can be achieved at high gain mode for small input signal levels. With IMD sinking technique, the input-referred IP3 is about 7.5 dBm for large interferences. For larger input signal levels, the input P1dB at high linear mode is -2.3 dBm.
A CMOS distributed amplifier with current reuse optimization
(2006)
Chou, Mei-Fen
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Tsou, Wen-An
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Dunn, Robert H.
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Huang, Hsiang-Lin
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Wen, Kuei-Ann
A CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption while retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only,12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-mu m CMOS technology. An analog behavior model is also developed for system-level simulation to shorten the design time and increase design quality for future integrated wide.-band transceivers.
A Decouple structured Gyroscope with Integrated Readout Circuit on Standard 0.18 mu m 1P6M CMOS Technology
(2016)
Chien, Chun-Lin
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Wen, Kuei-Ann
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A dual proof-mass structured gyroscope integrated with readout circuit have been proposed. The C to V stage is achieved by the differential difference amplifier (DDA) which has advantages of high gain, low temperature and process dependence. Chopper Stabilization (CHS) and Corrected Double Sampling (CDS) is used to suppress low-frequency noise and compensate DC offset. The gain of DDA is 25dB and power consumption of total readout circuit is 791 mu W. The mems part is fabricated with standard 1P6M 0.18um CMOS process and the mechanical sensitivity is 11.26aF/degrees/s. Chip area is 1.9x1.7mm(2).
A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with V(dd)/AM and V(dd)/PM Compensations in EER System
(2009)
Tsou, Wen-An
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Wuen, Wen-Shen
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Wen, Kuei-Ann
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An auto-biasing cascode class-E PA which can compensate the V(dd)/AM and V(dd)/PM distortion resulting from supply modulation has been proposed. The output voltage of auto-biasing control circuit is generated and varied linearly with PA's supply voltage so that the cascode transistor is degenerated into a resistance and the PA's nonlinear distortion can be compensated. The simulation result shows that the distortion is compensated evidently and the system co-simulation demonstrated that system EVM can be improved from -17 to -19dB. Also, the drain efficiency of the PA can be improved 15% within small supply voltage range.
A Design of CMOS Class-E Power Amplifier with Phase Correction for Envelope Elimination and Restoration (EER)/Polar Systems
(2010-01-01)
Tsou, Wen-An
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Wuen, Wen-Shen
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Wen, Kuei-Ann
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A circuit technique to correct V(dd)/PM distortion and improve efficiency as supply modulation of cascode class-E PAs has been proposed. The experimental result shows that the phase distortion can be improved from 20 degrees to 5 degrees. Moreover, a system co-simulation result demonstrated that the EVM can be improved from -17 dB to -19 dB.
A GENERALIZED FOUNDRY CMOS PLATFORM FOR CAPACITIVELY-TRANSDUCED RESONATORS MONOLITHICALLY INTEGRATED WITH AMPLIFIERS
(2010)
Chen, Wen-Chien
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Chen, Che-Sheng
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Wen, Kuei-Ann
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Fan, Long-Sheng
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Fang, Weileun
A generalized foundry CMOS-MEMS platform suited for integrated micromechanical resonator circuits have been developed for commercial multi-user purpose and demonstrated with a fast turnaround time and a variety of design flexibilities for resonator applications. With this platform, different configurations of capacitively-transduced resonators monolithically integrated with their associated amplifier circuits, spanning frequencies from 500kHz to 14.5MHz, have been realized with resonator Q\'s around 2,000. This platform specifically featured with various configurations of structural materials, different arrangements of mechanical boundary conditions, large transduction area, well-defined anchors, and performance enhancement scaling with IC fabrication technology, offers a variety of flexible design options suited for sensor and RF applications.
A Low Power Reconfigurable SAR ADC for CMOS MEMS Sensor
(2017-01-01)
Lin, Hao-Min
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Wen, Kuei-Ann
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a reconfigurable successive approximation register (SAR) Analog-to-Digital Converter (ADC) of which the resolution can be scaled from 9 to 12 bits for various inertial MEMS sensor applications. The dual supply voltage skill separating digital and analog voltage is implemented for achieving low power consumption. In addition, level shifter connects the interface between digital and analog domain. 3 bit segmented capacitor array are used to decrease the static error and glitches from MSB switching. In the provided 9 to 12 bits mode, this structure consumes 2.5, 2.8, 3.9 and 9.7 mu W and achieve 52.3, 57.7, 63.2 and 68.6 SNDR respectively, resulting in figure of merit (FoM) 148, 88.8, 66.3 and 88.4fJ/conversion-step.
A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion
(2009-12-01)
Chen, Chia-Pei
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Yang, Ming-Jen
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Huang, Hsun-Hsiu
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Chiang, Tung-Ying
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Chen, Jheng-Liang
A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the transmitter, the open-loop VCO modulation is adopted to save hardware and power consumption. The transmitter frequency drift in open-loop modulation and frequency offset between the receiver and the transmitter can be easily resolved by the proposed receiver architecture. All required building blocks of the proposed transceiver, except a RF matching network and a crystal, were implemented on a 4-mm(2) chip by a 0.18-mu m CMOS process. The receiver achieves -89-dBm sensitivity at 0.1% BER with 1-Mb/s data rate, and the transmitter delivers up to 0-dBm output power. The receiver and transmitter consume 13.3 mA and 10.7 mA, respectively, from a 1.8-V power supply.
A mismatch compensation circuit for CMOS quadrature VCO phase error
(2007)
Lee, Han-Jian
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Chen, Che-Sheng
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Wuen, Wen-Shen
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Wen, Kuei-Ann
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電子工程學系及電子研究所
This paper presents an analysis of phase errors; in LC quadrature VCO with a common-mode model. A mismatch compensation circuit is proposed to alleviate phase errors due to common-mode transconductance mismatch. With the compensation circuit, quardature phase errors and image rejection ration rate (IRR) are improved about 1.5 degrees and 4.7dB, respectively. The compensation circuit consumes 1.1mW.
A Monolithic CMOS MEMS Accelerometer with Chopper Correlated Double Sampling Readout Circuit
(2011)
Wang, Chun-Kai
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Chen, Che-Sheng
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Wen, Kuei-Ann
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/root Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.
A Monolithic CMOS MEMS Accelerometer with Low Noise Gain Tunable Interface in 0.18 mu m CMOS MEMS Technology
(2012)
Lin, Yi-Da
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Lin, Jian-Yuan
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Wang, Chun-Kai
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Fan, Long-Sheng
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Wen, Kuei-Ann
A monolithic capacitance accelerometer is fabricated in 0.18 mu m ASIC-compatible CMOS MEMS technology and, with the assistant of universal sensing system being developed in the proposed work. The new approach combines the Dual-Chopper amplifier and Correlated Double Sampling to alleviate 1/f noise and DC offset. The total noise equivalent acceleration is 13.49ug/root Hz under 500 Hz. The tunable sensitivity can be adjusted from 324.8 mV/fF to 17807.11mV/fF (differential mode) by the fully-differential variable gain amplifier (VGA).
A Monolithic CMOS/MEMS Accelerometer with Zero-g Calibration Readout Circuit
(2013-01-01)
Liu, Yu-Sian
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Huang, Chien-Jo
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Kuo, Fu-Yen
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Wen, Kuei-Ann
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Fan, Long-Sheng
A monolithic accelerometer design with zero-g calibration with TSMC 0.18 mu m mixed-signal 1P6M process is presented. On-chip digital offset calibration enables compensation of random mechanical offset in the sensor due to process variation. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is about 1.16 mW. The output noise is 26.85 mu g/v Hz at 1KHz.
A Multi-band Frequency Synthesizer for GSM/DCS/WIMAX/WLAN Applications with Ripple-free Circuit
(2010)
Chen, Po-Heng
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Chen, Che-Sheng
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Chou, Mei-Fen
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Wen, Kuei-Ann
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電子工程學系及電子研究所
This paper presents a fully integrated multi- band frequency synthesizer implemented in CMOS 0.18 mu m process with ripple-free circuit in a single loop. The synthesizer is designed for GSM/ DCS/WIMAX/WLAN (802.11a/b/g) systems applying to IQ phase based transceivers. The proposed synthesizer with ripple-free circuit can reduce the amplitude of control voltage ripple. The synthesizer performs the suppression of 31.4dB in the spectrum of reference-spur and the peak-to-peak jitter with 74% improvement compared to the conventional single loop synthesizer design.
A novel application of LDPC-based decoder for WiMAX dual-mode inner encoder
(2006)
Lin, Li-Hsieh
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Wen, Kuei-Ann
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
LDPC codes have recently received a lot of attention by their excellent error-correcting capability and have been adopted as an optional error correct coding scheme in WiMAX (802.16e) standard for mobility. In order to the low-complexity SOC (System-on-a-chip) design and multi-mode transmitter compatible, we proposed a novel application of LDPC decoder to substitute Viterbi decoder for convolutional encoder. The main character presented in this study is that the general two-decoder structure is replaced by one decoder. Our results indicate that the proposed scheme processes nice performance for mobile WiMAX system.
A Polar Modulated CMOS Class-E Amplifier with a Class-F Driver Stage
(2009)
Tsou, Wen-An
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Wuen, Wen-Shen
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Wen, Kuei-Ann
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a fully integrated polar modulated CMOS class-E amplifier in a 0.18 mu m CMOS process. The amplifier using the device-stacking topology is implemented with a self-biased control circuit, which allows the stacked device operating as a resistance, for linearizing the AM-AM and AM-PM distortion. The simulation result shows that the AM-PM distortion is reduced from 18 degrees to 3 degrees. The linearized class-E amplifier with the class-F driver stage can provide the maximum power gain of 21 dB, the maximum output power of 17 dBm, and the peak power-added efficiency (PAE) of 30% from the supply voltage of 2 V.
A Polar Modulated Tri-band Power Amplifier Using Flexible Substrate Based MEMS Switches
(2010-01-01)
Lai, Chung-Min
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Chao, Tzu-Yuan
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Tsou, Wen-An
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Chou, Mei-Fen
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Cheng, Yu-Ting
In this work, the phase compensation techniques by means of self-biasing control and an additional tuning capacitor for polar modulated tri-band Class-E power amplifier is proposed. The tri-band power amplifier operating at 2.3 similar to 2.7/3.3 similar to 3.8/5.1 similar to 5.8 GHz for WLAN and WiMAX applications adjusts low loss Micro-Electro-Mechanical-Systems (MEMS) switches to select the matching networks. The improvement of phase distortion and system relative constellation error (RCE) is 36.4 degrees and 8.9dB, respectively. Simulation results shows that the maximum power-added efficiency (PAE) of 34.9%, drain efficiency of 37.3%, and output power of 18.8dBm from 2.8V supply can be achieved in 0.18 mu m CMOS Technology.
A single-chip low-power tunable CMOS low-IF single-conversion ISM receiver
(2005)
Chen, Chia-Pei
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Li, Simon C.
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Kao, Hong-Sing
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Su, Chung-Chih
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Wen, Kuei-Ann
A single-chip tunable CMOS low-IF single-conversion receiver operated in the 915-MHz ISM band is proposed. A new 10.7-MHz IF section including a limiting amplifier and FM/FSK demodulator is employed. Near IF section sensitivity of -72 dBm, the demodulation constant of FM/FSK demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier reaches 80dB. With on-chip tunable components in low power LNA and LC-tank VCO circuit, the receiver measures a RF gain of 15dB at 915-MHz, sensitivity of -80dBm at 0.1% BER, IIP3 of -9dBm, and NF of 5dB with current consumption of 33mA and a chip area of 6 mm(2).
A unified behavior model of low noise amplifier for system-level simulation
(2006)
Hung, Chih-De
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Wuen, Wen-Shen
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Chou, Mei-Fen
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Wen, Kuei-Ann
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電子工程學系及電子研究所
This paper presents a unified RF behavior model that simultaneously predicts the effects of noise, nonlinearity, impedance matching and frequency response and that enables efficient and accurate system simulation. The proposed modeling approach allows characterizing the RF effects incrementally to reduce iteration. A Verilog-A behavior model for an ultra-wideband CMOS low noise amplifier is developed for fast and accurate system simulation. The system simulation results show that the behavior model agrees well with the transistor-level circuit with RMS error less than 0.79%. Ultimately, 87% reduction of simulation time is achieved.
An Active Guarding Circuit Design for Wideband Substrate Noise Suppression
(2008-11-01)
Chao, Hao-Ming
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Wuen, Wen-Shen
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Wen, Kuei-Ann
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電子工程學系及電子研究所
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友訊交大聯合研發中心
In this paper, an active guarding circuit is presented for wideband substrate noise suppression. A feed-forward compensation mechanism is proposed to extend the noise suppression bandwidth and to adjust the amplitude of phase-inversed noise cancellation current by introducing a zero and an amplitude controller. A noise decoupling mechanism is developed to provide a decoupling path and to sense the noise level for generating noise cancellation current. With substrate characterization, parameters of substrate network impedance, decoupling factor, and amplitude of noise cancellation current can be either obtained or determined. The active guarding circuit is implemented in a 90-nm CMOS process based on substrate characterization. The measured substrate noise suppression is better than -9 dB from dc to 250 MHz. The -3-dB suppression bandwidth is effectively extended to 1.2 GHz. The power consumption and circuit area are 2.5 mW and 20 mu m x 41 mu m, respectively.