Browsing by Author "Wu, CM"

Now showing 1 - 14 of 14

0.13 mu m low voltage logic based RF CMOS technology with 115GHz f(T) and 80GHz f(MAX)
(2003)
Guo, JC
;
Huang, CH
;
Chan, KT
;
Lien, WY
;
Wu, CM
Superior RF CMOS of 115GHz f(T) and 80GHz f(max) has been realized by 0.13mum low voltage logic based RF CMOS technology by aggressive device scaling and optimized layout. NFmin of 2.2dB at 10GHz is achieved even without deep N-well and ground-shielded signal pad. P,dB of near 10dBm can fit bluetooth requirement and 55% PAE at 2.4 GHz address the good potential of sub-100nm CMOS for low voltage RF power applications.
0.13-mu m low-kappa-Cu CMOS logic-based technology for 2.1-Gb high data rate read-channel
(2004-05-01)
Guo, JC
;
Lien, WY
;
Tsai, TL
;
Chen, SM
;
Wu, CM
High-performance analog/digital elements have been successfully fabricated bya 0.13-mum low-kappa-Cu logic-based mixed-signal CMOS process in a single chip to enable a 2.1-Gb/s read-channel for hard disk drives that is a record-high data rate supported by fully CMOS solution. The high-performance analog devices demonstrate superior drivability, matching, noise immunity, and reliability by a unique dual-gate oxide module to support the aggressive oxide thickness scaling and maintain promisingly good reliability in all aspects.
A new method for extracting the channel-length reduction and the gate-voltage-dependent series resistance of counter-implanted p-MOSFET's
(1997-12-01)
Wu, CM
;
Wu, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Based on the channel-resistance measurement, a new method for extracting the channel-length reduction (Delta L-jj) and the gate-voltage-dependent source/drain resistance (R-SD) of counter-implanted p-MOSFET's is proposed, in which the necessity of the applying substrate bias is demonstrated and an empirical relationship between poly-Si gate length (L-M) and device structure parameters for Delta L-jj extraction is provided, This is the first attempt to extract the basic parameters of counter-implanted p-MOSFET's with the LDD structure, Numerical analysis using two-dimensional (2-D) device simulator has been used to verify the proposed extraction method, Furthermore, an improved approach to extract R-SD is also presented, Both numerical analysis and experimental results show good accuracy of our proposed method.
A new method for extracting the counter-implanted channel profile of enhancement-mode p-MOSFET's
(1997-12-01)
Wu, CM
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new methodology is proposed to extract the nonuniform channel doping profile of enhancement mode p-MOSFET's with counter implantation, based on the relationship between device threshold voltage and substrate bias. A self-consistent mathematical analysis is developed to calculate the threshold voltage and the surface potential of counter-implanted long-channel p-MOSFET at the onset of heavy inversion, Comparisons between analytic calculation and two-dimensional (2-D) numerical analysis have been made and the accuracy of the developed analytic model has been verified, Based on the developed analytic model, an automated extraction technique has been successfully implemented to extract the channel doping profile. With the aid of a 2-D numerical simulator, the subthreshold current can be obtained by the extracted channel doping profile. Good agreements have been found with measured subthreshold characteristics for both long-and short-channel devices, This new extraction methodology can be used for precise process monitoring and device optimization purposes.
A reconfigurable architecture for DSP system-on-chip
(2001-07-01)
Dung, LR
;
Lee, YL
;
Wu, CM
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電控工程研究所
;
Institute of Electrical and Control Engineering
Digital signal processing (DSP) has been moving into the era of system-on-chip (SoC) design. Yet, the development of SoC architectures is rather intellectual-property (IP)-based and presents several challenges to designers, notably in the transformation of algorithms and the integration of IP cores. Tams, this paper employs Petri nets to model the DSP algorithms and presents a novel architecture for rapid design of digital signal processing. The architecture features a reconfigurable scheduler to dynamically schedule DSP operations onto processing elements and, thus, tolerates nondeterministic latencies of operations due to communication overhead and memory caching. Using the architecture, the designer can seamlessly plug in different IP cores to explore the alternative solutions and upgrade the architecture by reconfiguring the scheduler.
A simple transmission line de-embedding method for accurate RF CMOS noise modeling
(2004)
Guo, JC
;
Huang, CH
;
Lien, WY
;
Wu, CM
;
電子工程學系及電子研究所
We propose a simple method to de-embed the transmission line and pads' parasitics from the measured RF noise of multi-finger MOSFETs with aggressive gate length scaling down to 80 nm and 65 nm respectively. Good agreement has been realized between measurement and simulation in terms of S-parameters and NFmin (minimum noise figure) for RF CMOS devices with various finger numbers by using this novel de-embedding method. The extracted NFmin after de-embedding matches well with the published noise correlation matrix method but is relatively simple without resort to complicated matrices calculation.
Application of iterative explicit scheme to 1-D varied flows
(1996)
Hsu, CT
;
Yeh, KC
;
Wu, CM
;
土木工程學系
;
Department of Civil Engineering
Block-decoupling linear multivariable systems: Necessary and sufficient conditions
(1998-02-01)
Lin, CA
;
Wu, CM
;
電控工程研究所
;
Institute of Electrical and Control Engineering
We study block decoupling of linear multivariable systems under unity-feedback configuration. We consider plants which have unstable pole-zero coincidences and give necessary and sufficient conditions for the existence of the block decoupling controllers. The conditions are particularly simple for plants with only simple unstable pole-zero coincidences. An illustrative example is given. (C) 1998 Elsevier Science Ltd. All rights reserved.
Decoupling precompensation and optimal decoupling
(2001-01-01)
Lin, CA
;
Wu, CM
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電控工程研究所
;
Institute of Electrical and Control Engineering
We study decoupling control under a unity-feedback configuration for linear multivariable plants. We parametrize the set of all admissible decoupling precompensators. With the parametrization, it is shown that decoupling controller design is equivalent to a set of SISO controller designs. The parametrization is also used to establish a necessary and sufficient condition for the existence of a stable decoupling controller. Optimal decoupling controller design is proposed and the cost of decoupling is discussed.
High-sensitivity sensor based on surface plasmon resonance and heterodyne interferometry
(2003-07-01)
Wu, CM
;
Jian, ZC
;
Joe, SF
;
Chang, LB
;
交大名義發表
A common-path, heterodyne interferometric system for investigation of the phase variations under surface plasmon resonance (SPR) is presented. With the combination of SPR and total internal reflection (TIR), the system has the merits of avoiding direction change in the output light and increasing sensitivity. The system utilizes a pair of orthogonally linearly polarized beams with heterodyne frequency of 60 kHz as the light source. Because the two beams are perfectly collinear, the noises resulting from the ambient conditions are greatly reduced. Compared to reflectivity variation measurement, which is widely used in traditional SPR, the phase variation measurement using commonpath, heterodyne techniques is approximately an order of magnitude higher in sensitivity and thus can be used as a high-sensitivity-demanded biosensor. (C) 2003 Elsevier Science B.V. All rights reserved.
Necessary and sufficient conditions for existence of block decoupling controllers
(1996)
Lin, CA
;
Wu, CM
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
We study block decoupling of linear multivariable system under unity-feedback configuration. We give necessary and sufficient conditions for the existence of stabilizing block decoupling controllers. The conditions are simple and straightforward.
Preparation and mechanical properties of nitrile butadiene rubber/silicate nanocomposites
(2004-07-22)
Hwang, WG
;
Wei, KH
;
Wu, CM
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材料科學與工程學系
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Department of Materials Science and Engineering
Elastomer nanocomposites consisting of nitrile butadiene rubber (NBR) latex and layered silicates are prepared by a modified latex shear blending process aided with ball milling. The mode of dispersion of layered silicates in NBR is partially exfoliated and intercalated when the concentration of layered silicates is below 7.5 wt%, as evidenced by transmission electron microscopy and X-ray diffraction results. The tensile and tear mechanical properties are much higher than that of neat NBR. Specifically, the tensile and tear mechanical properties of the NBR/layered silicates increase by 200 and 60%, respectively. The decomposition temperature of the nanocomposites increases slightly. (C) 2004 Elsevier Ltd. All rights reserved.
Synergistic effect of compatibilizer in organo-modified layered silicate reinforced butadiene rubber nanocomposites
(2006-01-01)
Hwang, WG
;
Wei, KH
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Wu, CM
;
材料科學與工程學系
;
Department of Materials Science and Engineering
We have prepared nanocomposites of intercalated and exfoliated organosilicates in butadiene rubber (BR) by using a two-stage melt blending process. We used X-ray diffraction and transmission electron microscopy to examine, respectively, the intergallery spacing of the organosilicates and their dispersion in the BR. Marked enhancements in the mechanical and thermal properties of BR occurred when it incorporated < 10 parts of organosilicates and the loading ratio of the organosilicate to dicarboxylic acid-terminated butadiene oligomer was approximately three. In particular, the addition of 10 parts of organosilicate and 3 parts of compatibilizer in the BR led to a more than four-fold increase in the tensile strength, a 150% increase in modulus at 100% elongation (M 100), and 232 and 410% enhancements in the tear strength and elongation at break, respectively, relative to those of neat BR. The degradation temperature for the BR nanocomposite containing only a 10-part loading of organosilicate was 51 degrees C higher than that of neat BR; these increases reduced, however, to 9-13 degrees C upon the addition of the CTB compatibilizer. In addition, the relative water vapor permeabilities of the BR nanocomposites containing 10 parts of organosilicate- both in the presence and absence of the compatibilizer- reduced to 20% of that of the neat BR.
Uncertainty analysis of sediment transport formulas
(1996)
Yeh, KC
;
Deng, SL
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Wu, CM
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土木工程學系
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Department of Civil Engineering