Browsing by Author "Yang, JJ"

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A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's
(1999-07-01)
Chung, SS
;
Yang, JJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N-it) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N-it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N-it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices.
A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices
(2001)
Chung, SS
;
Chen, SJ
;
Yang, WJ
;
Yang, JJ
;
電子工程學系及電子研究所
In this paper, we present new results on the width dependent hot-carrier (HC) degradation for shallow-trench-isolated (STI) CMOS devices. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. New models and mechanisms are proposed to explain the width dependent degradation for both n-channel and p-channel MOSFET's, where new monitors are developed for both types of devices respectively. In fi-MOSFET's, the interface state generation at the STI-edge is enhanced for narrow width device. However, for p-MOSFET's, a two-dimensional channel shortening model is introduced. The channel shortening induced oxide damage is the dominant mechanism for the drain current degradation. Both are found to be strongly related to the mechanical stress on the border of the trench. This is a very crucial issue for the present and future CMOS ULSI using STI technologies.
An improved interface characterization technique for a full-range profiling of oxide damage in ultra-thin gate oxide CMOS devices
(2003)
Chen, SJ
;
Lin, TC
;
Lo, DK
;
Yang, JJ
;
Chung, SS
In this paper, an improved gate-diode technique has been developed for the interface characterization on both n- and p-MOSFET's with gate oxide in the direct tunneling regime. This method has been demonstrated successfully for measuring oxide damage in all of the channel, space-charge (or junction), and drain extension regions in 20Angstrom ultra-thin gate oxide devices. As an application of the present method, the lateral profile of localized oxide damage due to Negative Bias Temperature Instability (NBTI) or Hot Carrier (HC) effect has been demonstrated. It provides us an understanding of the correlation between the device degradation and various stress-induced oxide damage in CMOS devices.
Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack
(2006-03-01)
Chung, SS
;
Yeh, CH
;
Feng, HJ
;
Lai, CS
;
Yang, JJ
For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The ID degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which holetrap-induced V-T is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device ID degradation. In addition, the V-T rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N-2 content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.
Localization of NBTI-induced oxide damage in direct tunneling regime gate oxide pMOSFET using a novel low gate-leakage gated-diode (L-2-GD) method
(2002)
Chung, SS
;
Lo, DK
;
Yang, JJ
;
Lin, TC
;
電子工程學系及電子研究所
As gate oxide thickness reduces, previous reported methods can not work well for very thin gate oxide devices as a result of the measured leakage current through the gate oxide. For the first time, a novel Low gate Leakage Gate-Diode (L-2-GD) method has been developed for the interface characterization of MOSFET devices with gate oxide in the direct tunneling regime. Three-peak experimental results, as seen from DCIV measurement, can be easily obtained from this L-2-GD method. This method has been demonstrated successfully for the ultra-thin (12-20Angstrom) gate oxide device. Also, by using this new technique, the localized oxide damage due to NBTI or HC (Hot Carrier) stress effect can be identified simply from the measured drain currents. Therefore, this L-2-GD technique is well suited for the characterization of very thin gate oxide reliabilities, and in particular for the nano-scale CMOS devices.
Magnetic analysis of a micromachined magnetic actuator using the finite element method
(1999)
Ko, CH
;
Yang, JJ
;
Chiou, JC
;
Chen, SC
;
Kao, TH
In this paper, a parametrical method is developed to design a magnetic microactuator. The method is based on modeling the magnetic microactuator using the finite element analysis software that can be used to calculate the energy density and magnetic force. Here, the concept of design on experiments (DOE) is used to identify critical parameters that affect the performances of the electromagnetic microactuator. Numerical simulation results from a series of DOE have indicated that the dimension of core and the magnetic material block have the influence on planar electromagnetic actuators. When the length of the magnetic components is equal to that of outer diameter of coil circuit, we obtain the best efficiency in magnetic force. Furthermore, when we increase the thickness of the magnetic materials block or shorten the distance between the coils and magnetic material block, the magnetic force will increase dramatically. In addition, we can achieve a great magnetic force when the combination ratio of the length of the core is half of the magnetic material block. Simulation results have shown that electromagnetic actuators with high aspect ratio planar coil could sustain higher electrical current that consequently increases the magnetic force. During the realistic fabrication, the thick resist patterning and electroplating technologies is used to fabricate:the above-mentioned electromagnetic microactuator. Experimental results indicated that the magnetic force follows closely to the simulation results.
New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect-transistors
(2001-01-01)
Chung, SS
;
Chen, SJ
;
Yang, WJ
;
Yih, CM
;
Yang, JJ
In this study, width-dependent hot-carrier degradation in the p-channel metal-oxide-semiconductor held-effect transistors (p-MOSFETs) with shallow-trench-isolation (STI) is presented. Results show an enhanced drain current degradation with reducing the gate width. A new model and mechanism are proposed to explain the width-dependent hot-carrier (HC) degradation for p-MOSFETs. Based on a two-dimensional channel shortening concept, a new model is developed. The mechanical stress enhanced oxide damage at the STI edge, which will induce channel shortening, is the dominant mechanism for the drain current degradation of the devices after hot-carrier stress. This is a crucial issue for present and future complementary metaloxide semiconductor (CMOS) ultra-large-scale integration (ULSI), and in particular for high-density dynamic random-access memory (DRAM), fabricated using STI technologies.
Quantitative investigation of hot carrier induced drain current degradation in submicron drain-engineered metal-oxide-semiconductor field-effect-transistors
(2001-09-01)
Yang, JJ
;
Chung, SSS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Parameters, such as the total amount of hot carrier induced interface states and substrate current, are not sufficient to evaluate hot carrier reliability in drain-engineered metal-oxide-se mi conductor field-effect-transistors (MOSFETs). In this paper, for the first time, the distributions of hot carrier induced interface states are physically characterized and incorporated into two-dimensional device simulation to quantitatively study the structure-dependent drain current degradation in submicron MOSFETs, which give us insight into the relationship between degradation modes and device structures. The results show that the hot carrier induced series resistance effect in the sidewall spacer region plays an important role in drain-engineered MOSFETs. A different gate oxide thickness dependence of drain current degradation in thin gate oxide lightly-doped drain (LDD) MOSFETs is observed and is explained as the interface states enhanced series resistance effect in the LDD region.
The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology
(2004)
Chung, SS
;
Yeh, CH
;
Feng, SJ
;
Lai, CS
;
Yang, JJ
In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the I-D degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the I-D degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced V-T shifts are significant. The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage Current and an increase of DeltaV(T) in thin-oxide with reduced width.