Browsing by Author "Yeh, WK"

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A new tungsten gate metal oxide semiconductor capacitor using a chemical vapor deposition process
(1997-01-01)
Yeh, WK
;
Shiau, YC
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new process for tungsten gate metal oxide semiconductor (MOS) capacitors has been developed using chemical vapor deposition (CVD) of tungsten on a thin poly-Si layer of appropriate thickness. The poly-Si acts as a sacrificial layer and is consumed during the CVD of tungsten (W). This process yields a nearly pure W metal gate after Sill, reduction of WF6 at 300 degrees C. Compared with sputtered tungsten films, the CVD tungsten film has lower resistivity and lower intrinsic film stress. In addition, the CVD tungsten metal gate MOS capacitor has a lower interface state density (D-it) and a higher charge-to-breakdown (Q(bd)), than sputter-deposited tungsten gate MOS capacitors.
An efficient improvement for barrier effect of W-filled contact
(1996-02-01)
Yeh, WK
;
Chan, KY
;
Chang, TC
;
Tsai, MH
;
Chen, SH
A post chemical vapor deposition of tungsten (CVD-W) treatment by N-2 plasma is proposed to suppress the WAl12 formation during subsequent thermal annealing, which improves the thermal stability of W-filled contact. Selective CVD-W is employed to fill the contact hole. Following W deposition, in situ N-2 plasma treatment is performed prior to Al alloy metallization. It is shown that this post CVD-W treatment efficiently suppresses the formation of WAl12, resulting in an improvement of the barrier capability of W-filled contact.
Anomalous selective tungsten growth by chemical vapor deposition
(1996)
Mei, YJ
;
Chang, TC
;
Sheu, JD
;
Yeh, WK
;
Pan, FM
Selective tungsten chemical vapor deposition (W-CVD) is one of the most attractive technique for filling deep submicron contact hole and via hole for the ULSI application. In this work, we firstly find out the anomalous selective W growth for the contact hole. The tungsten only nucleates from the side ring of the contact hole bottom. Several predeposition treatments prior to W growth can improve this anomalous feature and excellently selective W growth can be achieved. Auger electron spectroscopy (AES) is utilized to investigate the interface of Si/W. A model has been proposed to explain this anomalous selective tungsten growth.
Characterization of diamond films grown on amorphous SiO2
(1996-04-01)
Chen, CF
;
Leu, SY
;
Chen, SH
;
Yeh, WK
;
交大名義發表
Continuous diamond film growth on SiO2 was achieved by an effective pretreatment. Carbon implantation and diamond powder abrasion were used to enhance diamond nucleation on SiO2. The possibility of using two gas mixtures (CH4-CO2 and CH4-H-2) in order to achieve the growth of continuous diamond films on SiO2 was examined. The diamond film growth rate obtained using the CH4-CO2 gas mixture was 0.6 mu m/h which is roughly three times higher than that of the CH4-H-2 gas mixture. CH4-H-2 gas mixtures had a lower etching reaction rate than that of CH4-CO2 gas mixtures. The higher etching rate of the CH4-CO2 gas mixture was considered to be due to a higher concentration of active carbon radicals or carbon-containing species in the plasma. Scanning electron microscopy (SEM) and optical emission spectroscopy (OES) indicated that active carbon radicals and carbon-containing species are the major cause of pits arising at the surface. Using CH4-H-2 gas mixtures at a low microwave power gave the optimum reaction conditions for depositing diamond films on SiO2 layers.
Chemical mechanical polishing for selective CVD-W
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
(1997-10-30)
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
(1997-10-30)
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Deposition properties of selective tungsten chemical vapor deposition
(1996-09-01)
Yeh, WK
;
Chen, MC
;
Wang, PJ
;
Liu, LM
;
Lin, MS
This work investigates the basic deposition properties of selective tungsten chemical vapor deposition (W-CVD) using the process of silane reduction of WF6 with the SiH4/WF6 flow rate ratio less than 0.6 over the temperature range 280-350 degrees C. Selective W-CVD was performed on a contact hole patterned silicon substrate with in situ NF3 plasma etching of the silicon substrate prior to the selective tungsten deposition. The W deposition rate, deposition selectivity and W film resistivity were investigated with respect to the SiH4 partial pressure, WF6 partial pressure, total (SiH4 + WF6) deposition pressure, as well as the flow rate of the hydrogen carrier gas. It was found that the deposition rate is proportional to the SiH4 partial pressure, With a constant SiH4/WF6 flow rate ratio, the deposition rate increases with total pressure. At given flow rates of SiH4 and WF6, the deposition rate and film resistivity are dependent on the flow rate of the carrier gas. The experimental results show that the reverse bias junction leakage for the wet etching pretreated W/p(+)-n junction diode is smaller than that of the plasma pretreated diode. On the other hand, the contact resistance of the Al/W/n(+)p diode is smaller than that of the Al/W/p(+)n diode.
Disordered Si/SiGe superlattices grown by ultrahigh vacuum chemical vapor deposition
(1996-02-01)
Chang, TC
;
Yeh, WK
;
Chang, CY
;
Jung, TG
;
Tsai, WC
A series of Si/Si1-xGex disordered superlattices with various degrees of disorder were grown in an ultrahigh vacuum chemical vapor deposition system (UHV/CVD). High-resolution double-crystal X-ray diffraction (HRXRD), and conventional cross-sectional transmission electron microscopy were used to evaluate the crystalline quality of these superlattices. A dynamical X-ray simulation program was employed to analyze the experimental rocking curves, Excellent matches between experimental rocking curves and simulated ones were obtained for all superlattices with various degrees of disorder.
Effect of surface pretreatment of submicron contact hole on selective tungsten chemical vapor deposition
(1996-01-01)
Yeh, WK
;
Chen, MC
;
Lin, MS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of various predeposition treatments of silicon substrates on selective tungsten chemical vapor deposition were investigated using the silane reduction process. The predeposition treatments include HF or buffered HF wet etch and/or NF3 plasma etch. The experimental results show remarkable differences in the initial nucleation of W and the smoothness of the W surface and the W/Si interface among the various treatments, as revealed by scanning electron microscope inspection and atomic force microscope analysis. Plasma etch leads to a rough W/Si interface while wet treatment with HF dip results in a fairly smooth interface. The experimental results show that better I-V characteristics for the W/n-Si Schottky contact can be obtained by the wet etch treatment prior to the W deposition. The reverse bias junction leakage for the wet etch pretreated W/p(+)n junction diode is smaller than that of the plasma pretreated diode. In addition, the substrate surface treatments were found to result in Si consumption of various degrees. (C) 1996 American Vacuum Society.
Efficient improvement of hot carrier-induced degradation for 0.1-mu m indium-halo nMOSFET
(2004-04-01)
Yeh, WK
;
Lin, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1-mum nMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900 degreesC) for a longer time.
Efficient improvement of hot-carrier-induced device's degradation for sub-0.1 mu m complementary metal-oxide-semiconductor field-effect-transistor technology
(2004-04-01)
Lin, JC
;
Yeh, WK
;
Lei, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effect of post-thermal annealing (PA) after In-halo and As-halo implantation on the reliability of sub-0.1 mum complementary metal-oxide-semiconductor field-effect-transistors was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving hot-carrier-induced device's degradation. The optimal results of device performance as well as of reliability can be obtained with post-annealing treatment performed at medium temperatures (e.g.. 900degreesC) for a longer time.
Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 mu m CMOSFET with 2-nm thin gate oxide
(2002-12-01)
Yeh, WK
;
Wang, WH
;
Fang, YK
;
Chen, MC
;
Yang, FL
Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BG-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 mum with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 mum FB-SOI pMOSFET is similar to that of the 0.1 mum BG-SOI pMOSFET.
Light emission from the porous boron delta-doped Si superlattice
(1996-02-01)
Chang, TC
;
Yeh, WK
;
Hsu, MY
;
Chang, CY
;
Lee, CP
We report the first study on the porous boron delta-doped Si superlattice. Visible photoluminescence (PL) was observed with multiple peaks from the porous boron delta-doped Si superlattice at room temperature. In the electroluminescence (EL) experiment, a bright yellow light emission was observed from the porous boron delta-doped Si superlattices. However, a weak red light emission was also observed from the conventional porous Si which is anodized at the same etching condition. As a result, the structure of the porous boron delta-doped Si superlattice has the ability of controlling the quantum size in porous Si and enhancing the light intensity from porous Si.
Low-frequency noise in partially depleted SOI MOSFETs operating from linear region to saturation region at various temperatures
(2004-04-01)
Chen, KM
;
Hu, HH
;
Huang, GW
;
Yeh, WK
;
Chang, CY
The low-frequency noise characteristics of partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) in silicon-on-insulator technology at various temperatures were investigated. For floating-body devices, a Lorentzian-like noise overshoot is observed due to the floating-body effect. The noise overshoot is dependent on temperature and bias, and can be reduced using a source-to-body-connected structure. At high temperature or high drain bias, the 1/f noise will be observed, and it is temperature-independent due to the trap-induced mobility fluctuation in the channel.
Photoluminescence from ordered and disordered Si-SiGe superlattices
(1996-10-01)
Chang, TC
;
Yeh, WK
;
Mei, YJ
;
Tsai, WC
;
Chen, YF
Ordered (Ord-SL) and disordered (Dis-SL) Si-SiGe superlattices are grown using ultrahigh vacuum chemical vapour deposition (UHVCVD). The results of cross-sectional transmission electron microscopy (XTEM) and high-resolution double crystal x-ray diffraction (HRXRD) indicate that high quality Si-SiGe superlattices can be achieved. Well-defined band-edge excitonic luminescence is observed for the Si0.86Ge0.14-Si superlattice. Stronger phosoluminescence (PL) is observed for the Si-SiGe disordered superlattice compared with the corresponding Si-SiGe ordered superlattice. Furthermore, PL peak energy of the Dis-SL shifts to lower value with respect to the peak position of the corresponding Ord-SL. The stronger intensity of the no-phonon (NP) peak and the red shift of the PL peak are possibly a result of two probable mechanisms: (i) the tunnelling effect and (ii) the formation of localized states.
Photoluminescence from ordered and disordered Si-SiGe superlattices
(1996-10-01)
Chang, TC
;
Yeh, WK
;
Mei, YJ
;
Tsai, WC
;
Chen, YF
Ordered (Ord-SL) and disordered (Dis-SL) Si-SiGe superlattices are grown using ultrahigh vacuum chemical vapour deposition (UHVCVD). The results of cross-sectional transmission electron microscopy (XTEM) and high-resolution double crystal x-ray diffraction (HRXRD) indicate that high quality Si-SiGe superlattices can be achieved. Well-defined band-edge excitonic luminescence is observed for the Si0.86Ge0.14-Si superlattice. Stronger phosoluminescence (PL) is observed for the Si-SiGe disordered superlattice compared with the corresponding Si-SiGe ordered superlattice. Furthermore, PL peak energy of the Dis-SL shifts to lower value with respect to the peak position of the corresponding Ord-SL. The stronger intensity of the no-phonon (NP) peak and the red shift of the PL peak are possibly a result of two probable mechanisms: (i) the tunnelling effect and (ii) the formation of localized states.
Selective tungsten CVD on submicron contact hole
(1995-12-01)
Yeh, WK
;
Chen, MC
;
Wang, PJ
;
Liu, LM
;
Lin, MS
This work investigates the deposition properties of selective chemically vapor-deposited tungsten for filling the deep sub-half micron contact holes using the process of silane reduction of tungsten hexafluoride. Low-resistivity tungsten with excellent selectivity and conformal coverage can be obtained with a SiH4/WF6 flow rate ratios less than 0.6 at deposition temperatures between 280 to 350 degrees C. Junction leakage and contact resistance of the AlSiCu/W/n(+)p and AlSiCu/W/p(+)n diodes as well as the electromigration properties of the AlSiCu/W/n(+)p structure were investigated.
The effect of thermal treatment on device characteristic and reliability for sub-100-nm CMOSFETs
(2004-06-01)
Yeh, WK
;
Fang, YK
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effect of post-thermal annealing after halo implantation on device characteristic and reliability of sub-100-nm CMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot-carrier-induced degradation. The best result of device performance and reliability was obtained by a post-thermal annealing treatment performed at medium temperatures (e.g., 900 degreesC) for a longer time (>1 min).