Browsing by Author "Yen, Li-Chen"

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Al-SiO2-Y2O3-SiO2-poly-Si Thin-Film Transistor Nonvolatile Memory Incorporating a Y2O3 Charge Trapping Layer
(2013)
Pan, Tung-Ming
;
Yen, Li-Chen
;
Mondal, Somnath
;
Lo, Chieh-Ting
;
Chao, Tien-Sheng
In this letter, we investigate the structural properties and electrical characteristics of the Al-SiO2-Y2O3-SiO2-poly-Si (AOYOP) thin-film transistor (TFT) nonvolatile memory device. The composition of Y2O3 charge-trapping layer was analyzed using X-ray photoelectron spectroscopy. The Y2O3 AOYOP TFT memory device exhibited a large memory window of 2.5 V, a long charge retention time of ten years with a minimal charge loss of similar to 15%, and a better endurance performance for P/E cycles up to 10(5). (c) 2013 The Electrochemical Society. All rights reserved.
Effect of Sensing Film Thickness on Sensing Characteristics of Dual-Gate Poly-Si Ion-Sensitive Field-Effect-Transistors
(2014-12-01)
Yen, Li-Chen
;
Tang, Ming-Tsyr
;
Tan, Chia-Ying
;
Pan, Tung-Ming
;
Chao, Tien-Sheng
We investigate the effect of sensing film thickness on the sensing characteristics of dual-gate (DG) poly-Si ion-sensitive field-effect transistors (ISFETs). The pH sensitivity (from 37.57 to 9.32 mV/pH) of the DG poly-Si ISFET device degrades with the increase in the sensing film thickness (from 20 to 120 nm), whereas hysteresis voltage (from 6.7 to 1.12 mV for a neutral to acid to alkaline to neural loop) and drift rate (from 13.47 to <3 mV/h at pH 7) improve accordingly. An improved hysteresis and drift phenomena are attributed to the reduction in top-gate capacitance of the sensing membrane, causing a smaller capacitive-coupling ratio (top-gate capacitance of sensing membrane to bottom-gate capacitance of tetraethylorthosilicate oxide).
Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-kappa Eu2O3 gate dielectrics
(2012-04-23)
Yen, Li-Chen
;
Hu, Chia-Wei
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Pan, Tung-Ming
In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu2O3 gate dielectric. High-kappa Eu2O3 LTPS-TFT annealed at 500 degrees C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm(2)/V-s, a small subthreshold swing of 142 mV/decade, and a high I-on/I-off current ratio of 1.34 x 10(7). These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu2O3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu2O3 LTPS-TFT device. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4705472]
High-kappa Eu2O3 and Y2O3 Poly-Si Thin-Film Transistor Nonvolatile Memory Devices
(2013-07-01)
Pan, Tung-Ming
;
Yen, Li-Chen
;
Huang, Sheng-Hao
;
Lo, Chieh-Ting
;
Chao, Tien-Sheng
In this paper, we have successfully fabricated low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) nonvolatile memory devices employing high-kappa Eu2O3 and Y2O3 films as the charge trapping layer. The LTPS-TFT memory device uses band-to-band tunneling-induced hot hole injection and gate Fowler-Nordheim injection as the program and erase methods, respectively. Compared with the Y2O3 film, the LTPS-TFT memory device using an Eu2O3 charge-trapping layer exhibited a lower subthreshold swing and a larger memory window, a smaller charge loss, and a better endurance performance, presumably because of the higher charge-trapping efficiency of the Eu2O3 film.
Improvement in pH Sensitivity of Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Sensors Using H-2 Sintering
(2014-03-01)
Yen, Li-Chen
;
Tang, Ming-Tsyr
;
Chang, Fang-Yu
;
Pan, Tung-Ming
;
Chao, Tien-Sheng
In this article, we report an improvement in the pH sensitivity of low-temperature polycrystalline-silicon (poly-Si) thin-film transistor (TFT) sensors using an H-2 sintering process. The low-temperature polycrystalline-silicon (LTPS) TFT sensor with H-2 sintering exhibited a high sensitivity than that without H-2 sintering. This result may be due to the resulting increase in the number of Si-OH2+ and Si-O- bonds due to the incorporation of H in the gate oxide to reduce the dangling silicon bonds and hence create the surface active sites and the resulting increase in the number of chemical reactions at these surface active sites. Moreover, the LTPS TFT sensor device not only offers low cost and a simple fabrication processes, but the technique also can be extended to integrate the sensor into other systems.
Influence of Postdeposition Annealing on Physical and Electrical Properties of High-k Yb2TiO5 Gate Dielectrics
(2010)
Pan, Tung-Ming
;
Yen, Li-Chen
;
Chiang, Chien-Hung
;
Chao, Tien-Sheng
;
電子物理學系
The structure and electrical properties of a high-k Yb2TiO5 gate dielectric deposited on Si(100) substrates through reactive cosputtering were investigated. X-ray diffraction, X-ray photoelectron spectroscopy and atomic force microscopy were used to study the morphological and chemical features of these films as functions of the growth conditions. The Yb2TiO5 dielectrics annealed at 800 degrees C exhibited a thinner capacitance equivalent thickness, a lower gate leakage current, a smaller density of interface state, and a relatively lower hysteresis voltage compared to those at other annealing temperatures. These results are attributed to the formation of a rather well-crystallized Yb2TiO5 structure and composition.
Label-free and real-time detection of ferritin using a horn-like polycrystalline-silicon nanowire field-effect transistor biosensor
(2016-07)
Yen, Li-Chen
;
Pan, Tung-Ming
;
Lee, Chiang-Hsuan
;
Chao, Tien-Sheng
;
電子物理學系
In this paper, we used the horn-like polycrystalline-silicon nanowire field-effect transistor (poly-Si NW FET) biosensors to detect ferritin. It employs the trapezoidal-shape dummy gate structure fabricated at the spacer wire process to form the shape of horn-like nanowires. The horn-like poly-Si NW FET using a channel length of 2 mu m exhibited better electrical characteristics, such as a smaller threshold voltage of 1.1 V and a higher I-on/I-off of 3.47 x 10(5), compared to other channel lengths. In addition, the horn-like poly-Si NW FET sensor exhibited a high sensitivity of 133.47 mV/pH exceeding the Nernst limit. This result is attributed to the higher capacitive-coupling ratio (top-gate capacitance to bottom-gate capacitance). Moreover, we used a horn-like poly-Si NW FET biosensor to detect the ferritin in buffer solution due to its label-free, real-time, and high-sensitive. We modified 3-aminopropyltriethoxysilane on the SiO2/Si3N4/SiO2 stacked surface followed by glutaraldehyde functionalized, and the ferritin antibodies were immobilized on the aldehyde terminal. While the serum ferritin antigen was prepared in the buffer, the results indicated that the sensor could detect serum ferritin below 50 pg/mL in a micro-fluidic channel. (C) 2016 Elsevier B.V. All rights reserved.
Label-free Detection of Prostate Specific Antigen Using a Silicon Nanobelt Field-effect Transistor
(2012-05-01)
Wu, Chi-Chang
;
Pan, Tung-Ming
;
Wu, Chung-Shu
;
Yen, Li-Chen
;
Chuang, Cheng-Keng
In this study, we proposed a silicon nanobelt field-effect transistor (FET) to detect prostate specific antigen (PSA). The nanobelt FET device displayed n-channel depletion characteristics. The immobilization of prostate specific antibody (anti-PSA) molecules was attached onto the nanobelt FET surface by using the aldehyde groups of glutaraldehyde linked to the amino groups of 3-aminopropyltriethoxysilane (APTES). The shift in the drain current vs time curves of a nanobelt FET biosensor revealed that the electrical signal had a logarithmic relationship with respect to the concentration of the PSA, and detection capability was estimated in the 5 pg/mL level. To enhance the sensitivity of a nanobelt FET biosensor, this biosensor was designed by inserting arginine molecules between glutaraldehyde and APTES. Therefore, the detection capability of the developed sensor was extended to 50 fg/mL. Also, the relationship between the current shift and the logarithm of PSA concentration was exhibited linearity in the range 50 fg/mL - 500 pg/mL. The excellent electrical results of this label-free PSA nanobelt FET biosensor suggested that such biosensor might be potentially useful tools for biological research and future prostate cancer screening.
Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILC
(2013-08-01)
Chen, Yi-Hsuan
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Yen, Li-Chen
;
Chang, Tien-Shun
;
Chiang, Tsung-Yu
;
Kuo, Po-Yi
It is known that metal-induced lateral crystallization (MILC) thin-film transistors (TFTs) exhibit higher on-state current, steeper subthreshold slope, and lower minimum leakage than solid-phase-crystallization TFTs. In this letter, we propose a tunneling TFT (T-TFT) fabricated by MILC method for the first time. The MILC T-TFTs demonstrate a lower subthreshold swing, similar to 232 mV/decade, than the other T-TFTs and a high ON/OFF ratio > 10(6) at V-DS = 1 V without any hydrogen-related plasma treatment. These improvements can be due to the reduction of defects at grain boundaries and the channel direction parallel to grains. The polycrystalline silicon T-TFTs fabricated in this letter show a great promise for low standby power circuits, drivers of active-matrix liquid crystal displays, and 3-D integrated circuits applications in the future.
Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array
(2012-06-01)
Wang, Kuan-Ti
;
Hsueh, Fang-Chang
;
Lu, Yu-Lun
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Chiang, Tsung-Yu
;
Wu, Yi-Hong
This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 mu s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.
Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors
(2012-08-01)
Wu, Yi-Hong
;
Lin, Je-Wei
;
Lu, Yi-Hsien
;
Kuo, Rou-Han
;
Yen, Li-Chen
"In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n(+) region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n(+) region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n(+) region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n(+) region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of V-G is less than half of V-D"
Structural and Electrical Properties of High-k HoTiO3 Gate Dielectrics
(2010)
Pan, Tung-Ming
;
Yen, Li-Chen
;
Hu, Chia-Wei
;
Chao, Tien-Sheng
;
電子物理學系
We developed a high-k HoTiO3 gate dielectric deposited on Si (100) through reactive cosputtering. They found that the HoTiO3 dielectrics annealed at 800 degrees C exhibited excellent electrical properties such as high capacitance value, small density of interface state, almost no hysteresis voltage, and low leakage current. This phenomenon is attributed to the decrease in intrinsic defect due to the formation of well-crystallized HoTiO3 structure and composition.
Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures
(2011-07-01)
Wu, Yi-Hong
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Kuo, Po-Yi
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Lu, Yi-Hsien
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Chen, Yi-Hsuan
;
Chiang, Tsung-Yu
This paper reports the impacts of NH(3) plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. OFF-state currents may be improved by increasing the oxide overetching depth. The ON/OFF current ratio may be also improved by increasing the oxide overetching depth. The NH(3) plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH(3) plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (< 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. OFF-state currents can be improved by increasing L(mask), even when the oxide overetching depth and the gate oxide thickness are changed.