Browsing by Author "Yu, DS"

Now showing 1 - 18 of 18

3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-kappa dielectric on 1P6M-0.18 mu m-CMOS
(2004)
Yu, DS
;
Chin, A
;
Laio, CC
;
Lee, CF
;
Cheng, CF
For the first time, we demonstrate 3D integration of self-aligned IrO2(Hf)/LaAlO3/GOI CMOSFETs above 0.18 pm Si CMOSFETs. At EOT=1.4nm, the novel IrO2(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO3/Si devices have high electron and hole mobilities of 203 and 67 cm(2)/Vs. On the 3D structure the LaAlO3/GOI shows even higher 389 and 234 cm(2)/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.
Al2O3-Ge-On-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates
(2004-03-01)
Yu, DS
;
Huang, CH
;
Chin, A
;
Zhu, CX
;
Li, MF
High-kappa, A1(2)O(3)/Ge-on-insulator (GOI) n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates were fabricated. At 1.7-nm equivalent-oxide-thickness (EOT), the A1(2)O(3)-GOI with metal-like NiSi and NiGe gates has comparable gate leakage current with A1(2)O(3)-Si MOSFETs. Additionally, A1(2) O-3-GOI C-MOSFETs with fully NiSi and NiGe gates show 1.94 and 1.98 times higher electron and hole mobility, respectively, than A1(2)O(3)-Si devices, because the electron and hole effective masses of Ge are lower than those of Si. The process with maximum 500 degreesC rapid thermal annealing (RTA) is ideal for integrating metallic gates with high-kappa to minimize interfacial reactions and crystallization of the high-kappa material, and oxygen penetration in high-kappa MOSFETs.
Bias-temperature instability on fully silicided-germanided gates/high-k Al2O3CMOSFETs
(2005)
Liao, CC
;
Yu, DS
;
Cheng, CF
;
Chin, A
;
電子工程學系及電子研究所
We have studied bias-temperature instability (BTI) on fully nickel-silicided (NiSi) and germanided (NiGe) gates on high-k Al2O3 n metal oxide semiconductor field effect transistors (MOSFETs) and pMOSFETs, respectively. At an equivalent oxide thickness of 1.7 nm, the NiSi/Al2O3 pMOSFETs and NiGe/Al2O3 nMOSFETs have a comparable threshold voltage (V-t) change of -34 and 33 mV at 85&DEG; C and 10 MV/cm stress for 1 h. This result is different from the more severe negative BTI (NBTI) degradation measured in oxynitride pMOSFET than positive BTI (PBTI) in nMOSFET. The extrapolated maximum voltage for 10 years' lifetime is 1.16 and -1.12 V from NiSi-NiGe/Al2O3 complementary MOSFETs (CMOSFETs) that can barely meet the required 1 V operation with 10% safety margin. Further improvement is still required because the 1.8 nm oxynitride CMOSFETs have higher 10 years' lifetime operation voltages of 2.48 and -1.52 V for PBTI and NBTI, respectively. © 2005 The Electrochemical Society. All rights reserved.
Device level characterization for energy bandgap of strain-relaxed SiGe and oxide/SiGe barrier height
(2004)
Huang, CH
;
Yu, DS
;
Chin, A
;
Chen, WJ
;
McAlister, SP
From the interface state density with energy plot measured by capacitance-voltage characteristics, we have derived the energy bandgap of strain-relaxed Si1-xGex (x: 0.4 and 0.7) for the first time at the device level, because the allowed states increases sharply near the conduction and valence bandedges. We find that the energy bandgap of SiGe is reduced from 0.90 to 0.83 eV as the Ge composition increases from Si0.6Ge0.4 to Si0.3Ge0.7. In contrast, similar oxide/Si1-xGex conduction-band barrier heights of similar to3.1 eV have been obtained for both SiGe cases using Fowler-Nordheim tunneling. These results are in good agreement with published theoretical and experimental data from material level characterization. The device level characterization is especially important because the SiGe composition and material property may be altered after thermal cycles for device fabrication. (C) 2004 The Electrochemical Society.
Fully silicided NiSi and germanided NiGe dual gates on SiO2 n- and p-MOSFETs
(2003-12-01)
Yu, DS
;
Wu, CH
;
Huang, CH
;
Chin, A
;
Chen, WJ
We have fabricated the fully silicided NiSi and germanided NiGe dual gates n- and p-MOSFETs on 1.9 nm thick SiO2 gate dielectric. The extracted work functions of fully NiSi and NiGe gates from thickness-dependent flat band voltage were 4.55 and 5.2 eV respectively, which may provide possible wide work function tuning using NiSi1-xGex. In additional to the lower gate current than Al gate n- and p-MOSFETs, the fully silicided NiSi and germanided NiGe gates MOSFETs show electron and hole mobilities close to universal mobility values with special advantage of process compatible to current VLSI fabrication line.
Fully silicided NiSi and germanided NiGe dual gates on SiO2/Si and Al2O3/Ge-on-insulator MOSFETs
(2003)
Huang, CH
;
Yu, DS
;
Chin, A
;
Wu, CH
;
Chen, WJ
We demonstrate for the first time fully silicided NiSi (4.55eV) and germanided NiGe (5.2eV) dual gates on 1.9nm-SiO2/Si and Al2O3/Ge-On-Insulator (GOI) MOSFETs (EOT = 1.7nm). In additional to the comparable gate current and time-to-breakdown with AI gate C-MOSFETs, the fully NiSi and NiGe gates on SiO2/Si show mobility close to universal mobility while on Al2O3/GOI show similar to2.0X higher peak electron and hole mobility than Al on Al2O3/Si with special advantage of NiSi and NiGe compatible to current VLSI process line.
High hole mobility of Al2O3 mosfets on dislocation free Ge-on-insulator wafers
(2004)
Chin, A
;
Yu, DS
;
Wu, CH
;
Huang, CH
;
Chen, WJ
The much degraded mobility, high-kappa dielectric crystallization, and EOT reduction after processing are the primary limitations of high-kappa gate dielectric MOSFETs. We have fabricated the high-kappa Al2O3 MOSFET on Geon-Insulator to enhance the hole mobility. The measured hole mobility with 1.7 nm EOT is 73 cm(2)/Vs at E-eff of 1 MV/cm, which is 2.5 times and 1.3 times higher than and Al2O3/Si control devices and SiO2/Si universal mobility, respectively. In additional to good dielectric reliability, the low temperature process (less than or equal to500degreesC) can also avoid high-kappa dielectric crystallization and EOT reduction by O-2 or moisture penetration through high-kappa dielectric.
High performance metal-gate/high-kappa, MOSFETs and GaAs compatible RF passive devices on Ge-on-Insulator tlechnology
(2004)
Chin, A
;
Kao, HL
;
Yu, DS
;
Liao, CC
;
Zhu, C
We propose and demonstrate a new VLSI structure using high performance metal-gate/high-kappa MOSFETs and high-Q RF passive devices on Ge-on- Insulator (GOI) platform. In additional to high RF performance passive devices on insulating Si formed by ion implantation. the metal-gate/(La)AiO(3)/GOI MOSFETs have 1.7-2.0X improved electron and hole mobility with the merits of minimizing interfacial reaction., high-kappa crystallization, Fermi-level pinning, and impurity diffusion due to low thermal budget of 500 degrees C RTA.
High work function IrxSi gates on HfAlON p-MOSFETs
(2006-02-01)
Wu, CH
;
Yu, DS
;
Chin, A
;
Wang, SJ
;
Li, MF
We have fabricated the fully silicided IrxSi-gated p-MOSFETs on HfAlON gate dielectric with 1.7-mn equivalent oxide thickness. After 950 degrees C rapid thermal annealing, the fully IrxSi/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm(2)/V.s, and the advantage of being process compatible to the current VLSI fabrication line.
High-density RF MIM capacitors using high-k La2O3 dielectrics
(2004)
Yang, MY
;
Yu, DS
;
Chin, A
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The integrity of the metal-insulator-metal (MM) capacitor with high-k La2O3 dielectrics formed using a 400degreesC back-end process was investigated. A very high capacitance per unit area of 9.2 fF/mum(2) was achieved for La2O3 MIM capacitors at 1 MHz, significantly reducing the chip size of radio frequency (rf) circuits. A mathematical derivation, involving measured S parameters, yielded the small voltage-dependent capacitance (DeltaC/C) less than or equal to 100 ppm at 1 GHz, indicating that the precision capacitor circuit can be applied in the rf regime. Furthermore, such a high capacitance density can be maintained as the frequency is increased from 10 KHz to 20 GHz with a large Q factor greater than or equal to90. (C) 2004 The Electrochemical Society.
Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference
(2005)
Yu, DS
;
Chin, A
;
Wu, CH
;
Li, MF
;
Zhu, C
Metallic diffusion through high-K HfO(2), caused by high temperature metal-nitride decomposition, was reduced by using robust HfAlON. Useful dual effective work-function (phi(m,eff)) of 4.25 and 5.15 eV are obtained in TaTb(0.2)N/HfAlON and Ir/HfAlON at 1.7nm EOT. Good dual phi(m,eff) of 4.15 and 4.9 eV are also obtained in Yb(x)Si/HfAlON and Ir(x)Si/HfAlON FUSI-gates by reduced metal diffusion at lower temperature.
Low voltage high speed SiO(2)/AlGaN/AlLaO(3)/TaN memory with good retention
(2005)
Chin, A
;
Laio, CC
;
Chen, C
;
Chiang, KC
;
Yu, DS
To improve trapping using deeper well AlGaN (chi=3.8eV), lower voltage drop in high-K AlLaO(3) barrier (kappa=23), and smaller erase current by large Delta E(c) of AILaO(3)/TaN, the SiO(2)/AlGaN/AlLaO(3)/TaN devices show good 85 degrees C memory integrity of low +/- 10V 1ms P/E, large 3.9V initial Delta V(th) and 2.4V extrapolated 10-year retention. A fast 100ps P/E of +/- 11V still gives 3.0V initial Delta V(th) and 1.6V 10-year retention.
Performance and potential of germanium on insulator field-effect transistors
(2006-05-01)
Yu, DS
;
Kao, HL
;
Chin, A
;
McAlister, SP
;
電子工程學系及電子研究所
The performance of field-effect transistors may be improved by increasing the channel mobility. Strained Si can accomplish this but Ge is another option. Here we show data for germanium-on-insulator (GOI) devices and also describe the simple bonding process which was used in the device fabrication. The GOI devices show better mobilities than their Si counterparts. We also show data for some metal-gate/high-kappa dielectric devices on a GOI layer fabricated on a processed Si wafer. Here the GOI structure and processing does not alter the underlying Si devices and yet gives devices whose mobilities exceed those of Si devices. Simulations support the view that the improved performance results from the mobility enhancement and that the performance should also hold for submicron devices. (c) 2006 American Vacuum Society.
Physics and modeling of Ge-on-Insulator MOSFETs
(2005)
Chin, A
;
Kao, HL
;
Tseng, YY
;
Yu, DS
;
Chen, CC
We have used process and device simulation tools (T-Supreme and Medici) to analyze the measured DC characteristics of Ge-on-Insulator (GOI) MOSFETs. The GOI devices have higher drive current than do their Si counterparts, due to the smaller effective mass (m) and smaller Ge energy bandgap - however this also causes a larger off-state I(ds) leakage current. The simulations predict that the GOI MOSFETs have better RF gain and noise performance compared with Si devices. This is important for high speed operation as down-scaling continues.
Reducing AC power consumption by three-dimensional integration of Ge-on-insulator CMOS on 1-poly-6-metal 0.18 mu m Si MOSFETs
(2005)
Yu, DS
;
Liao, CC
;
Chen, CC
;
Lee, CF
;
Cheng, CF
We have used three-dimensional (3D) integration to reduce the ac power consumption in interconnects, which is the most severe issue beyond the dc power arising from the gate dielectric leakage current. From a direct calculation of the ac power consumption using an electromagnetic method, we show that both the ac power consumption and maximum operation frequency can be improved by integrating an additional integrated circuit layer. The 3D integration was realized by Ge-on-insulator (GOI) complementary metal oxide semiconductor field effect transistors (CMOSFETs) on 1-poly-6-metal (1P6M) 0.18 mu m Si devices, where little performance degradation was measured in the lower layer 0.18 mu m Si MOSFETs, due to the inherent low thermal budget (500 degrees C rapid thermal anneal) of the GOI processing. The drive current of the 3D GOI n- and p-MOSFETs was more than double that of the control Si devices, providing another advantage of the approach. (c) 2005 The Electrochemical Society. All rights reserved.
The copper contamination effect of Al2O3 gate dielectric on Si
(2004)
Liao, CC
;
Cheng, CF
;
Yu, DS
;
Chin, A
;
電子工程學系及電子研究所
We have studied the Cu contamination effect on 4.2 nm thick Al2O3 metal-oxide semiconductor (MOS) capacitors with an equivalent-oxide thickness (EOT) of 1.9 nm. In contrast to the large degradation of gate oxide integrity of control 3.0 nm SiO2 MOS capacitors contaminated by Cu, the 1.9 nm EOT Al2O3 MOS devices have good Cu contamination resistance with only small degradation of gate dielectric leakage current, charge-to-breakdown, and stress-induced leakage current. This strong Cu contamination resistance is similar to oxynitride (with high nitrogen content), but the Al2O3 gate dielectric has the advantage of higher K value and lower gate dielectric leakage current. (C) 2004 The Electrochemical Society.
The effect of IrO2-IrO2-Hf-LaAlO3 gate dielectric on the bias-temperature instability of 3-d GOI CMOSFETs
(2005-06-01)
Yu, DS
;
Liao, CC
;
Cheng, CF
;
Chin, A
;
Li, MF
We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-κ/Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 μ m CMOSFETs. The devices used IrO2-IrO2-Hf dual gates and a high-κ LaAlO3 gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-κ/GOI p-and n-MOSFETs displayed threshold voltage (V-t) shifts of 30 and 21 mV after 10 MV/cm, 85 &DEG; C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-κ-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.
Three-dimensional metal gate-high-kappa-GOI CMOSFETs on 1-poly-6-metal 0.18-mu m Si devices
(2005-02-01)
Yu, DS
;
Chin, A
;
Liao, CC
;
Lee, CF
;
Cheng, CF
We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-Insulator (GOI) CMOSFETs above 0.18-mum Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO3-GOI p-MOSFETs and IrO2-Hf-LaAlO3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm(2)/Vs respectively, without depredating the underneath 0.18-mum Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.