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公開日期標題作者
1-五月-1999Process optimization and integration for silicon oxide intermetal dielectric planarized by chemical mechanical polishLin, CF; Tseng, WT; Feng, MS; 材料科學與工程學系; Department of Materials Science and Engineering
1-十二月-1998Process optimization of plasma-enhanced chemical vapor deposited passivation thin films for improving nonvolatile memory IC performanceLin, CF; Tseng, WT; Feng, MS; 材料科學與工程學系; Department of Materials Science and Engineering
1-十二月-1998Process optimization of plasma-enhanced chemical vapor deposited passivation thin films for improving nonvolatile memory IC performanceLin, CF; Tseng, WT; Feng, MS; 材料科學與工程學系; Department of Materials Science and Engineering
1-二月-1997Re-examination of pressure and speed dependences of removal rate during chemical-mechanical polishing processesTseng, WT; Wang, YL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1998ULSI multi-layer thin film passivation processes for improving cache memory performanceLin, CF; Tseng, WT; Feng, MS; Chang, YF; Hsu, JJ; 材料科學與工程學系; Department of Materials Science and Engineering
22-六月-1999A ULSI shallow trench isolation process through the integration of multilayered dielectric process and chemical-mechanical planarizationLin, CF; Tseng, WT; Feng, MS; Wang, YL; 材料科學與工程學系; Department of Materials Science and Engineering
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