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Issue DateTitleAuthor(s)
1-Sep-1993BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERINGLEE, CL; JEN, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Feb-1992BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATELEE, CL; JEN, CW; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-Jun-1994CMOS THRESHOLD GATE AND NETWORKS FOR ORDER STATISTIC FILTERINGLEE, CL; JEN, CW; 電控工程研究所; Institute of Electrical and Control Engineering
1-Mar-1992DATA FLOW REPRESENTATION OF ITERATIVE ALGORITHMS FOR SYSTOLIC ARRAYSJEN, CW; KWAI, DM; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1981DEPLETION WIDTHS OF THE METAL-INSULATOR SEMICONDUCTOR (MIS) STRUCTUREJEN, CW; LEE, CL; LEI, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Oct-1988DESIGN OF A SYSTOLIC ARRAY SYSTEM FOR LINEAR STATE-EQUATIONSJOU, SJ; JEN, CW; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-Nov-1989DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSORLIU, CM; JEN, CW; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-Jun-1990DESIGN OF ONE-DIMENSIONAL SYSTOLIC-ARRAY SYSTEMS FOR LINEAR STATE-EQUATIONSJEN, CW; JOU, SJ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-Oct-1992THE EFFICIENT MEMORY-BASED VLSI ARRAY DESIGNS FOR DFT AND DCTGUO, JI; LIU, CM; JEN, CW; 資訊工程學系; 電子工程學系及電子研究所; Department of Computer Science; Department of Electronics Engineering and Institute of Electronics
1-Sep-1994EFFICIENT TIME-DOMAIN SYNTHESIS OF PIPELINED RECURSIVE FILTERSLAN, CP; JEN, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Sep-1987ELLIPSOMETRY MEASUREMENTS ON SIO2-FILMS FOR THICKNESSES UNDER 200-AHO, JH; LEE, CL; JEN, CW; LEI, TF; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1994HARDWARE SHARING IN TREE-STRUCTURE QMF BANKSLEE, HR; JEN, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Aug-1995A LOW-COST RASTER ENGINE FOR VIDEO GAME, MULTIMEDIA PC AND INTERACTIVE TVCHEN, CL; LIANG, BS; JEN, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-1995A low-cost raster engine for video game, multimedia PC and interactive TVCHEN, CL; LIANG, BS; JEN, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Oct-1986MOTA - A MOSFET TIMING SIMULATORJOU, SJ; JEN, CW; SHEN, WZ; LEE, CL; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-Dec-1989MULTI-DIMENSIONAL PARALLEL COMPUTING STRUCTURES FOR REGULAR ITERATIVE ALGORITHMSJEN, CW; KWAI, DM; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-Jan-1993A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORMGUO, JI; LIU, CM; JEN, CW; 資訊工程學系; 電子工程學系及電子研究所; Department of Computer Science; Department of Electronics Engineering and Institute of Electronics
1-May-1995A NOVEL CORDIC-BASED ARRAY ARCHITECTURE FOR THE MULTIDIMENSIONAL DISCRETE HARTLEY TRANSFORMGUO, JI; LIU, CM; JEN, CW; 資訊工程學系; 電控工程研究所; Department of Computer Science; Institute of Electrical and Control Engineering
1993A NOVEL MEMORY ARCHITECTURE FOR VIDEO SIGNAL PROCESSORHUNG, JS; LIN, CH; JEN, CW; 電控工程研究所; Institute of Electrical and Control Engineering
1-Jan-1994A NOVEL VLSI ARRAY DESIGN FOR THE DISCRETE HARTLEY TRANSFORM USING CYCLIC CONVOLUTIONGUO, JI; LIU, CM; JEN, CW; 交大名義發表; National Chiao Tung University
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