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公開日期標題作者
1-十二月-2019Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD TechnologyChung, Yun-Yan; Lu, Kuan-Cheng; Cheng, Chao-Ching; Li, Ming-Yang; Lin, Chao-Ting; Li, Chi-Feng; Chen, Jyun-Hong; Lai, Tung-Yen; Li, Kai-Shin; Shieh, Jia-Min; Su, Sheng-Kai; Chiang, Hung-Li; Chen, Tzu-Chiang; Li, Lain-Jong; Wong, H-S Philip; Jian, Wen-Bin; Chien, Chao-Hsin; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-八月-2020Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ CooptimizationChiang, Hung-Li; Chen, Tzu-Chiang; Song, Ming-Yuan; Chen, Yu-Sheng; Chiu, Jung-Piao; Chiang, Katherine; Manfrini, Mauricio; Cai, Jin; Gallagher, William J.; Wang, Tahui; Diaz, Carlos H.; Wong, H. -S. Philip; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrateCheng, Chao-Ching; Chung, Yun-Yan; Li, Ming-Yang; Lin, Chao-Ting; Li, Chi-Feng; Chen, Jyun-Hong; Lai, Tung-Yen; Li, Kai-Shin; Shieh, Jia-Min; Su, Sheng-Kai; Chiang, Hung-Li; Chen, Tzu-Chiang; Li, Lain-Jong; Wong, H-S Philip; Chien, Chao-Hsin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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