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公開日期標題作者
2008The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technologyHsieh, E. R.; Chang, Derrick W.; Chung, S. S.; Lin, Y. H.; Tsai, C. H.; Tsai, C. T.; Ma, G. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Dimensional Dependences of the Dynamic-NBTI with 1.2 nm N20-ISSG oxynitridesLai, Chao Sung; Huang, D. C.; Chung, S. S.; 電機學院; College of Electrical and Computer Engineering
1-一月-2014New Observations on the Regular and Irregular Noise Behavior in a Resistance Random Access MemoryChen, Scott C. H.; Huang, Y. J.; Chung, S. S.; Lee, H. Y.; Chen, Y. S.; Chen, F. T.; Gu, P. Y.; Tsai, M. -J.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Reliability of ALD Hf-based high K gate stacks with optimized interfacial layer and pocket implant engineeringMao, A. Y.; Lin, W. M.; Yang, Cw.; Hsieh, Y. S.; Cheng, L. W.; Lee, G. D.; Tsai, C. T.; Chung, S. S.; Ma, G. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2012Suppressing Device Variability by Cryogenic Implant for 28-nm Low-Power SoC ApplicationsYang, C. L.; Tsai, C. H.; Li, C. I.; Tzeng, C. Y.; Lin, G. P.; Chen, W. J.; Chin, Y. L.; Liao, C. I.; Chan, M.; Wu, J. Y.; Hsieh, E. R.; Guo, B. N.; Lu, S.; Colombeau, B.; Chung, S. S.; Chen, I. C.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006Twin-GD: A new twin gated-diode measurement for the interface characterization of ultra-thin gate oxide MOSFET's with EOT down to 1nmLee, G. D.; Chung, S. S.; Mao, A. Y.; Lin, W. M.; Yang, C. W.; Hsieh, Y. S.; Chu, K. T.; Cheng, L. W.; Tai, H.; Hsu, L. T.; Lee, C. R.; Meng, H. L.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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