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公開日期標題作者
2013Design and Optimization Methodology for 3D RRAM ArraysDeng, Yexin; Chen, Hong-Yu; Gao, Bin; Yu, Shimeng; Wu, Shih-Chieh; Zhao, Liang; Chen, Bing; Jiang, Zizhen; Liu, Xiaoyan; Hou, Tuo-Hung; Nishi, Yoshio; Kang, Jinfeng; Wong, H. -S. Philip; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2013Metal-Gate/High-kappa/Ge nMOS at Small CET With Higher Mobility Than SiO2/Si at Wide Range Carrier DensitiesLiao, C. C.; Ku, T. C.; Lin, M. H.; Zeng, Lang; Kang, Jinfeng; Liu, Xiaoyan; Chin, Albert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Recommended Methods to Study Resistive Switching DevicesLanza, Mario; Wong, H-S Philip; Pop, Eric; Ielmini, Daniele; Strukov, Dimitri; Regan, Brian C.; Larcher, Luca; Villena, Marco A.; Yang, J. Joshua; Goux, Ludovic; Belmonte, Attilio; Yang, Yuchao; Puglisi, Francesco M.; Kang, Jinfeng; Magyari-Kope, Blanka; Yalon, Eilam; Kenyon, Anthony; Buckwell, Mark; Mehonic, Adnan; Shluger, Alexander; Li, Haitong; Hou, Tuo-Hung; Hudec, Boris; Akinwande, Deji; Ge, Ruijing; Ambrogio, Stefano; Roldan, Juan B.; Miranda, Enrique; Sune, Jordi; Pey, Kin Leong; Wu, Xing; Raghavan, Nagarajan; Wu, Ernest; Lu, Wei D.; Navarro, Gabriele; Zhang, Weidong; Wu, Huaqiang; Li, Runwei; Holleitner, Alexander; Wurstbauer, Ursula; Lemme, Max C.; Liu, Ming; Long, Shibing; Liu, Qi; Lv, Hangbing; Padovani, Andrea; Pavan, Paolo; Valov, Ilia; Jing, Xu; Han, Tingting; Zhu, Kaichen; Chen, Shaochuan; Hui, Fei; Shi, Yuanyuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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