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公開日期標題作者
1-九月-2008An on-chip test structure and digital measurement method for statistical characterization of local random variability in a processMukhopadhyay, Saibal; Kim, Keunwoo; Jenkins, Keith A.; Chuang, Ching-Te; Roy, Kaushik; 交大名義發表; National Chiao Tung University
1-九月-2008Optimal design of triple-gate devices for high-performance and low-power applicationsChiang, Meng-Hsueh; Lin, Jeng-Nan; Kim, Keunwoo; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2009Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology RoadmapWei, Lan; Deng, Jie; Chang, Li-Wen; Kim, Keunwoo; Chuang, Ching-Te; Wong, H. -S. Philip; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008Stable High-Density FD/SOI SRAM with Selective Back-Gate Bias Using Dual Buried OxideKim, Keunwoo; Kuang, Jente B.; Gebara, Fadi; Ngo, Hung C.; Chuang, Ching-Te; Nowka, Kevin J.; 交大名義發表; National Chiao Tung University
1-十二月-2009TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved StabilityKim, Keunwoo; Kuang, Jente B.; Gebara, Fadi H.; Ngo, Hung C.; Chuang, Ching-Te; Nowka, Kevin J.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 5 筆資料，總共 5 筆