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顯示 1 到 15 筆資料，總共 15 筆
公開日期標題作者
1-一月-2013Cache Capacity Aware Thread Scheduling for Irregular Memory Access on Many-Core GPGPUsKuo, Hsien-Kai; Yen, Ta-Kan; Lai, Bo-Cheng Charles; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2015A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUsLai, Bo-Cheng Charles; Kuo, Hsien-Kai; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2013A Distributed Thread Scheduler for Dynamic Multithreading on Throughput ProcessorsYen, Ta-Kan; Kuo, Hsien-Kai; Lai, Bo-Cheng Charles; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013A Distributed Thread Scheduler for Dynamic Multithreading on Throughput ProcessorsYen, Ta-Kan; Kuo, Hsien-Kai; Lai, Bo-Cheng Charles; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Enhancing Data Reuse in Cache Contention Aware Thread Scheduling on GPGPULu, Chin-Fu; Kuo, Hsien-Kai; Lai, Bo-Cheng Charles; 交大名義發表; National Chiao Tung University
2011FDPrior: A Force-Directed Based Parallel Partitioning Algorithm for Three Dimensional Integrated Circuits on GPGPUChen, Wan-Jing; Kuo, Hsien-Kai; Chiu, Tsou-Han; Lai, Bo-Cheng Charles; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012A Highly Parallel Design for Irregular LDPC Decoding on GPGPUsChiu, Tsou-Han; Kuo, Hsien-Kai; Lai, Bo-Cheng Charles; 交大名義發表; National Chiao Tung University
1-一月-2013A Locality-Aware Dynamic Thread Scheduler for GPGPUsHuang, Yu-Hao; Tseng, Ying-Yu; Kuo, Hsien-Kai; Yen, Ta-Kan; Lai, Bo-Cheng Charles; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013MEMORY CAPACITY AWARE NON-BLOCKING DATA TRANSFER ON GPGPULiu, Hao-Wei; Kuo, Hsien-Kai; Chen, Kuan-Ting; Lai, Bo-Cheng Charles; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
12-七月-2016A Quantitative Method to Data Reuse Patterns of SIMT ApplicationsLai, Bo-Cheng Charles; Platero, Luis Garrido; Kuo, Hsien-Kai; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2014A Read-Write Aware DRAM Scheduling for Power Reduction in Multi-Core SystemsLai, Chih-Yen; Pan, Gung-Yu; Kuo, Hsien-Kai; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2014Reducing Contention in Shared Last-Level Cache for Throughput ProcessorsKuo, Hsien-Kai; Lai, Bo-Cheng Charles; Jou, Jing-Yang; 交大名義發表; National Chiao Tung University
2012Thread Affinity Mapping for Irregular Data Access on Shared Cache GPGPUKuo, Hsien-Kai; Chen, Kuan-Ting; Lai, Bo-Cheng Charles; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2016Unified Designs for High Performance LDPC Decoding on GPGPULai, Bo-Cheng Charles; Lee, Chia-Ying; Chiu, Tsou-Han; Kuo, Hsien-Kai; Chang, Chun-Kai; 交大名義發表; National Chiao Tung University
2013考慮快取記憶體層級的產率處理器執行續映射方法論郭玹凱; Kuo, Hsien-Kai; 周景揚; 賴伯承; Jou, Jing-Yang; Lai, Bo-Cheng; 電子工程學系 電子研究所
顯示 1 到 15 筆資料，總共 15 筆