瀏覽 的方式： 作者 Liao, Wei-Nan
顯示 1 到 3 筆資料，總共 3 筆
| 公開日期 | 標題 | 作者 |
| 1-一月-2013 | A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control | Liao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2013 | A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist | Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2012 | 40奈米1.0Mb 6T管線化靜態隨機存取記憶體與三步階升壓型字元線和位元線降壓和適應性電壓偵測 | 廖偉男; Liao, Wei-Nan; 莊景德; Chuang, Ching-Te; 電子研究所 |
