瀏覽 的方式: 作者 Lu, Chien-Yu

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公開日期標題作者
1-五月-2015A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-AssistLu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2012A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-AssistLu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
五月-2016A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-lineWu, Shang-Lin; Lu, Chien-Yu; Tu, Ming-Hsien; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2013A Disturb-Free Subthreshold 9T SRAM Cell With Improved Performance and Variation ToleranceLu, Chien-Yu; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSILu, Chien-Yu; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2012A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing TracingTu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Lu, Chien-Yu; Lin, Yuh-Jiun; Wang, Meng-Hsueh; Huang, Huan-Shun; Lee, Kuen-Di; Shih, Wei-Chiang (Willis); Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014抗變異奈米互補式金氧半導體靜態隨機存取記憶體設計盧建宇; Lu, Chien-Yu; 莊景德; Chuang, Ching-Te; 電子工程學系 電子研究所