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顯示 1 到 7 筆資料，總共 7 筆
公開日期標題作者
1-八月-1999An all-digital phase-locked loop (ADPLL)-based clock recovery circuitHsu, TY; Shieh, BJ; Lee, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002An efficient modeling codec architecture for binary shape codingLiu, TM; Shieh, BJ; Lee, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-1999A generalized prediction method for modified memory-based high throughput VLC decoder designLee, YS; Shieh, BJ; Lee, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1998A high throughput variable length decoder with modified memory based architectureShieh, BJ; Lee, YS; Lee, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2000A high-throughput memory-based VLC decoder with codeword boundary predictionShieh, BJ; Lee, YS; Lee, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004A low-power group-based VLD designLiu, CH; Shieh, BJ; Lee, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2001A new approach of group-based VLC codec system with full table programmabilityShieh, BJ; Lee, YS; Lee, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 7 筆資料，總共 7 筆