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公開日期標題作者
2014A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOCDhong, Sang; Guo, Richard; Kuo, Ming-Zhang; Yang, Ping-Lin; Lin, Cheng-Chung; Huang, Kevin; Wang, Min-Jer; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2014A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS ApplicationLin, Mu-Shan; Tsai, Chien-Chun; Chang, Chih-Hsien; Huang, Wen-Hung; Hsu, Ying-Yu; Yang, Shu-Chun; Fu, Chin-Ming; Chou, Mao-Hsuan; Huang, Tien-Chien; Chen, Ching-Fang; Huang, Tze-Chiang; Adham, Saman; Wang, Min-Jer; Shen, William Wu; Mehta, Ashok; 交大名義發表; National Chiao Tung University
2014A 16kB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOSKuo, Ming-Zhang; Hsieh, Henry; Dhong, Sang; Yang, Ping-Lin; Lin, Cheng-Chung; Tseng, Ryan; Huang, Kevin; Wang, Min-Jer; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Custom 6-R, 2-or 4-W Multi-Port Register Files in an ASIC SOC with a DVFS Window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS TechnologyHsieh, Henry; Dhong, Sang H.; Lin, Cheng-Chung; Kuo, Ming-Zhang; Tseng, Kuo-Feng; Yang, Ping-Lin; Huang, Kevin; Wang, Min-Jer; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 4 筆資料，總共 4 筆