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公開日期標題作者
2004Comparison of oxide breakdown progression in ultra-thin oxide SOI and bulk pMOSFETsChan, CT; Kuo, CH; Tang, CJ; Chen, MC; Wang, TH; Lu, SH; Hu, HC; Chen, TF; Yang, CK; Lee, MT; Wu, DY; Chen, JK; Chien, SC; Sun, SW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm rangeChung, SS; Feng, HJ; Hsieh, YS; Liu, A; Lin, WM; Chen, DF; Ho, JH; Huang, KT; Yang, CK; Cheng, O; Sheng, YC; Wu, DY; Shiau, WT; Chien, SC; Liao, K; Sun, SW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETsWang, TH; Tsai, CW; Chen, MC; Chan, CT; Chiang, HK; Lu, SH; Hu, HC; Chen, TF; Yang, CK; Lee, MT; Wu, DY; Chen, JK; Chien, SC; Sun, SW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxideChung, SS; Chen, SJ; Yang, CK; Cheng, SM; Lin, SH; Sheng, YC; Lin, HS; Hung, KT; Wu, DY; Yew, TR; Chien, SC; Liou, FT; Wen, F; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 4 筆資料，總共 4 筆