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顯示 1 到 6 筆資料，總共 6 筆
公開日期標題作者
1-一月-2013An Area-Efficient BCH Codec with Echelon Scheduling for NAND Flash ApplicationsYang, Chi-Heng; Chen, Yi-Hsun; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012An Efficient BCH Decoder with 124-bit Correctability for Multi-Channel SSD ApplicationsTsai, Hung-Yuan; Yang, Chi-Heng; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012A Fully Parallel BCH Codec with Double Error Correcting Capability for NOR Flash ApplicationsChu, Chia-Ching; Lin, Yi-Min; Yang, Chi-Heng; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2015An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting CapabilityYang, Chi-Heng; Lin, Yi-Min; Chang, Hsie-Chia; Lee, Chen-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2011A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory DevicesLin, Yi-Min; Yang, Chi-Heng; Hsu, Chih-Hsiang; Chang, Hsie-Chia; Lee, Chen-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014應用於NAND型快閃記憶體系統之BCH編解碼器之研究楊其衡; Yang, Chi-Heng; 張錫嘉; Chang, Hsie-Chia; 電子工程學系 電子研究所
顯示 1 到 6 筆資料，總共 6 筆