1. 目前位置：

瀏覽 的方式： 作者 Yang, Yu-Ming

跳到： 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
或是輸入前幾個字：  
顯示 1 到 9 筆資料，總共 9 筆
公開日期標題作者
2010Analog Placement and Global Routing Considering Wiring SymmetryYang, Yu-Ming; Jiang, Iris Hui-Ru; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
2015Criticality-Dependency-Aware Timing Characterization and AnalysisYang, Yu-Ming; Tam, King Ho; Jiang, Iris Hui-Ru; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011INTEGRA: Fast Multi-Bit Flip-Flop Clustering for Clock Power Saving Based on Interval GraphsJiang, Iris H. -R.; Chang, Chih-Long; Yang, Yu-Ming; Tsai, Evan Y. -W.; Chen, Lancer S. -F.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2012INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power SavingJiang, Iris Hui-Ru; Chang, Chih-Long; Yang, Yu-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2015iTimerC 2.0: Fast Incremental Timing and CPPR AnalysisLee, Pei-Yu; Jiang, Iris Hui-Ru; Li, Cheng-Ruei; Chiu, Wei-Lun; Yang, Yu-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014iTimerC: Common Path Pessimism Removal Using Effective Reduction MethodsYang, Yu-Ming; Chang, Yu-Wei; Jiang, Iris Hui-Ru; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012Novel Pulsed-Latch Replacement Based on Time Borrowing and Spiral ClusteringChang, Chih-Long; Jiang, Iris Hui-Ru; Yang, Yu-Ming; Tsai, Evan Yu-Wen; Chen, Aki Sheng-Hua; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2014PushPull: Short-Path Padding for Timing Error Resilient CircuitsYang, Yu-Ming; Jiang, Iris Hui-Ru; Ho, Sung-Ting; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015針對奈米積體電路之時序分析與最佳化楊喻名; Yang, Yu-Ming; 江蕙如; Jiang, Iris Hui-Ru; 電子工程學系 電子研究所
顯示 1 到 9 筆資料，總共 9 筆