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Investigation of Pillar-Concave Structure for Low-Temperature Cu-Cu Direct Bonding in 3-D/2.5-D Heterogeneous Integration
(2020-08-01)
Chou, Tzu-Chieh
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Yang, Kai-Ming
;
Li, Jian-Chen
;
Yu, Ting-Yang
;
Yang, Yu-Tao
With the advantage of high surface-roughness tolerance, the pillar-concave Cu-Cu direct bonding without chemical-mechanical planarization (CMP) is investigated in detail, including the mechanism of thermal compensation, analysis of roughness, bonding strength, and bonding reliability. With the special design of Cu bond structure, excellent bonding results can be achieved under low thermal budget (150 degrees C for 1 min, atmosphere) with even high roughness of bonding surface. In addition, the pillar-concave scheme applied to fan-out panel-level package (FOPLP) has been demonstrated, showing the high feasibility of this scheme to realize applications in heterogeneous integration.
Transient Thermal Damage Simulation for Novel Location-Controlled Grain Technique in Monolithic 3D IC
(2019-01-01)
Chen, Pin-Jun
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Shen, Chih-Ming
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Yang, Chih-Chao
;
Tai, Ming-Chi
;
Lo, Wei-Chung
In this research, Finite Element Method (FEM) is used to simulate transient thermal conduction in the monolithic three-dimensional integrated circuit (3DIC) with a novel location-controlled-grain (LCG) technique. Through this method, the impact of laser flux, amorphous Si thickness and interlayer dielectric (ILD) thickness on that model can be investigated. Furthermore, with the assistance of thermal damage simulation, we can utilize the optimal process parameters in this state-of-the-art technique to accelerate the development of advanced semiconductor technologies.
Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators
(2019-01-01)
Hsieh, Ping-Yi
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Chang, Yi-Jui
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Chen, Pin-Jun
;
Chen, Chun-Liang
;
Yang, Chih-Chao
Monolithic 3D back-end of line (BEOL) FinFET switch arrays are demonstrated in large single crystalline Si islands (2.56 mu m(2)), whose location, size and shape are determined by design. Details of the improved location-controlled-grain (LCG) technique are presented. A voltage regulator implemented with the BEOL switch arrays using external control signals shows better theoretical figure of merit (FOM) of 0.089ns than 2D voltage regulators of 0.43ns.
Non-Planarization Cu-Cu Direct Bonding and Gang Bonding with Low Temperature and Short Duration in Ambient Atmosphere
(2019-01-01)
Chou, Tzu-Chieh
;
Yang, Kai-Ming
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Li, Jian-Chen
;
Yu, Ting-Yang
;
Chung, Ying-Ting
Low temperature (150 degrees C) and short duration Cu-Cu direct bonding, without planarization, and gang bonding approaches are demonstrated with excellent bond strength, electrical characteristics, and reliability. The concept is based on the high stress-led inducing deformation and internal friction to achieve low temperature bonding. In addition, the bonding structure has the advantage of high roughness tolerance on surface without CMP requirement. Compared to current products using Cu-Cu direct bonding at 350-400 degrees C with long duration and vacuum requirement, the breakthrough of proposed schemes provides the feasibility for product realization in 3D integration packaging.
Low Temperature Copper-Copper Bonding of Non-Planarized Copper Pillar With Passivation
(2020-08-01)
Tsai, Yi-Chieh
;
Hu, Han-Wen
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Low-thermal-budget (180 degrees C for 15 sec) Cu pillar to Cu pillar bonding with Pd passivation under the atmosphere is developed without any planarization pretreatment before the bonding process. The bonded structure is investigated with material analysis, electrical measurement and reliability test. The results show that although the Cu pillar has a high roughness surface due to the electroplating process with a high deposition rate, Cu atoms can still diffuse and connect through the passivation layer and perform the low-thermal-budget Cu pillar direct bonding. Low specific contact resistance and stable resistance of daisy chain shown in the reliability test reveal the excellent bonding quality and integrity. This Cu-Cu bonding method is therefore favorable for chip stacking technology development in 3D packaging domain.
Evaluation of Metal/Polymer Adhesion and Highly Reliable Four-Point Bending Test Using Stealth Dicing Method in 3-D Integration
(2020-06-01)
Yang, Yi-Lun
;
Ito, Hiroyuki
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Kim, Young Suk
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Ohba, Takayuki
;
Chen, Kuan-Neng
The adhesion between metal and polymer layer was studied using four-point bending tests. It was shown that as the annealing temperature increased, oxidation binding increased, which decreased adhesion and reduced the value. A new four-point bending test sample prepared using the stealth dicing method with a 100 & x0025; success rate was proposed for the first time. With samples prepared with stealth dicing, the region where crack extension occurred was smaller after the stress test. Less crack extension generated less loading on the samples. Owing to the coefficient of thermal expansion (CTE) mismatch after increasing the temperature in a highly accelerated stress test (HAST), a void formed in stealth dicing was made close to the interface between the silicon layer and the polymer layer after the stress test, and less crack extension occurred compared with samples kept at room temperature. The smaller loading force guarantees much more stable measurement with a higher success rate after the stress tests. The stealth dicing method can be applied to other structures, such as redistribution layers (RDLs).
An RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applications
(2018-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Shen, Wen-Wei
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Huang, Shin-Yi
;
Kuo, Tzu-Ying
Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.
Optimization of laser release process for throughput enhancement of fan-out wafer-level packaging
(2018-01-01)
Lee, Chia-Hsin
;
Su, Jay
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Liu, Xiao
;
Wu, Qi
;
Lin, Jim-Wein
Fan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 mu m thick) with coefficient of thermal expansion of 8 ppm/degrees C were treated by selected laser release layers. After deposition of 0.05-mu m Ti/0.15 mu m Cu on the glass carrier, passivation of around 8 mu m was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-mu m reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.
Adhesion Property of Polyimide and Passivation Layer for Polymer/metal Wafer-level Hybrid Bonding in 3D Integration
(2018-01-01)
Lu, Cheng-Hsien
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Kho, Yi-Tung
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Yang, Yu-Tao
;
Chen, Yu-Pei
;
Chen, Chiao-Pei
In this paper, the four-point bending method experiments were carried out with different polyimides and passivation layers for realization of adhesion property below 400 degrees C. Three types of passivation layers, thermal oxide, tetraethoxysilane (TEOS) oxide, silicon nitride, and three types of polyimides, with hydrophobic silane, with hydrophilic silane and without silane, and annealing temperature were all considered in this paper. Moreover, the relation between adhesion strength and surface roughness is discussed. Finally, a low thermal budget (250-375 degrees C) polyimide/metal hybrid bonding scheme with good stress release was proposed for future hybrid bonding applications.
Adhesion Properties of Electroplating Process Between Polyimide and Metal Layer for Polymer/Metal Hybrid Bonding
(2020-01-01)
Lu, Cheng-Hsien
;
Yang, Yi-Lun
;
Chen, Chiao-Pei
;
Tsai, Bin-Ling
;
Chen, Kuan-Neng
This article investigates the adhesion properties between the polyimide layers and the Ti/Cu layer after the electroplating process. The adhesion strength was evaluated by the four-point bending system, and the influence factors were confirmed by using different electroplating times and currents. The fracture interface after the four-point bending measurement was characterized, and the interface spectrum between the polyimide and the Ti/Cu layer was analyzed. The results showed that the modified polyimide-like material has better adhesion performance than the conventional polyimide. Moreover, the mechanism of degradation was proposed. As a result, the modified polyimide-like material can be applied in electroplating, a redistribution layer (RDL) formation, and packaging at the back-end-of-line processes.

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