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🏛️國立陽明交通大學機構典藏

Access type: Metadata onlyAuthor: search.filters.author.Chen, MC

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    Formation of NiSi-silicided p(+)n shallow junctions using implant through silicide and low temperature furnace annealing
    (2003-01-01)
    Wang, CC
    ;
    Lin, CJ
    ;
    Chen, MC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    NiSi-silicided p(+)n shallow junctions are fabricated using BF2+ implantation into/through thin NiSi silicide layer (ITS technology) followed by low temperature furnace annealing (from 550 to 800degreesC). The NiSi film agglomerates following a thermal annealing at 600degreesC, and may result in the formation of discontinuous islands at a higher temperature. The incorporation of fluorine atoms in the NiSi film can retard the formation of film agglomeration and thus improve the film's thermal stability. A forward ideality factor of about 1.02 and a reverse current density of about 1nA/cm(2) can be attained for the NiSi(310Angstrom)/p(+)n junctions fabricated by BF2+ implantation at 35 keV to a dose of 5x10(5) cm(-2) followed by a 650degreesC thermal annealing; the junction formed is about 60nm measured from the NiSi/Si interface. Activation energy measurements show that the reverse bias junction currents are dominated by the diffusion current, indicating that most of the implanted damages can be recovered after annealing at a temperature as low as 650degreesC.
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    Comparisons of link adaptation based scheduling algorithms for the WCDMA system with high speed downlink packet access
    (2004-01-01)
    Wang, LC
    ;
    Chen, MC
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    The wideband code division multiple access (WCDMA) system with high speed downlink packet access (HSDPA) is an important next generation wireless system. By adopting adaptive modulation, efficient scheduling, and hybrid automatic repeat request technologies, it can support data rates up to 10 Mbps in the mobile cellular environment. Among these techniques, the scheduling algorithm plays a key role in realizing the HSDPA concept A good scheduling algorithm should consider all the important factors including channel impact, delay issue, and fairness. In this paper, we suggest a fairness index to examine the fairness performance of current link adaptation based scheduling algorithms, including the maximum CA, round robin, proportional fair, and exponential rule schedulers. When supporting multi-type services, we find that the fairness performance of current scheduling algorithms, including the round robin scheduler, can be improved further even though the round robin scheduler is viewed as the scheduler of the greatest fairness. Thus, we are motivated to develop a new scheduling algorithm, namely the queue-based exponential rule scheduler. Through simulations, we show that in the context of multi-type services the fairness performance of the queue-based exponential rule scheduler can outperform all the schedulers in the time-multiplexing fashion, while maintaining good throughput and delay performance.
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    Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO2 high-k gate stacks
    (2005-08-01)
    Wu, WH
    ;
    Chen, MC
    ;
    Tsui, BY
    ;
    How, YT
    ;
    Yao, LG
    This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.
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    Formation of NiSi-silicided p(+)n shallow junctions by BF2+ implantation into/through silicide and rapid thermal annealing
    (2005-01-01)
    Wang, CC
    ;
    Wu, YK
    ;
    Wu, WH
    ;
    Chen, MC
    ;
    電子工程學系及電子研究所
    NiSi-silicided p(+) n shallow junctions are fabricated by BF2+ implantation into/through a thin NiSi silicide layer, followed by rapid thermal annealing (RTA). The NiSi film starts to show agglomeration after RTA at 650degreesC, which may result in the formation of discontinuous islands at higher temperatures. The incorporation of fluorine atoms in the NiSi film can retard the film agglomeration making the film stable up to 800degreesC. A forward ideality factor very close to unity and a reverse bias current density of 0.6 nA/cm(2) can be attained for the NiSi(31 nm)/p(+)n junctions fabricated by BF2+ implantation to a dose of 5 x 10(15) cm(-2) at 35 keV, followed by RTA for 30 s at 650degreesC; the junction formed is about 37 nm measured from the NiSi/Si interface. Activation energy measurement shows that the reverse bias junction currents are dominated by the diffusion current, which indicates that most of the implanted damage can be recovered by RTA at temperatures as low as 650degreesC.
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    Effects of thermal N-2 annealing on passivation capability of sputtered Ta(-N) layers against Cu oxidation
    (1998-11-01)
    Chuang, JC
    ;
    Chen, MC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The effects of thermal N-2 annealing on the passivation capability of sputtered Ta and Ta-nitride [Ta(-N)] layers against Cu oxidation in a 200 Angstrom Ta(-N) covered Ta(-N)/Cu/SiO2/Si structures was investigated. The N-2 annealed Ta layers revealed degradation in passivation capability, presumably due to grain growth of the Ta passivation layer. In contrast, the nitrogen-doped Ta-nitride layers showed a contrary trend. For the Ta-nitride layer with 23.5 atom % of nitrogen, passivation capability was effectively improved by N-2 annealing at 300 degrees C. For the Ta-nitride layer with 30.5 atom % of nitrogen, N-2 annealing at higher temperatures (500-700 degrees C) was necessary to improve the passivation capability. The healing of sputtering damage of Ta-nitride passivation layers by the thermal N-2 annealing was responsible, presumably, for the improvement of passivation capability.
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    Thermal stability of W-contacted junction diodes
    (1996-06-01)
    Yeh, WK
    ;
    Chan, KY
    ;
    Chang, TC
    ;
    Chen, MC
    ;
    Lin, MS
    This work investigates the thermal stability of W-contacted p(+)n junction diodes, in which the tungsten contact was formed by selective chemical vapor deposition (CVD) or sputtering process. Reaction of Al and CVD-W at elevated temperature leads to the formation of WAl12, and the barrier capability of CVD-W film was dependent on the consumption of W. The sputter-W film has a columnar structure and contains a higher content of oxygen. The presence of oxygen retarded the formation of WAl12 and thus enhanced the thermal stability of the Al/W/Si structure. However, degradation of the Al/sputter-W (100 nm)/p(+)n diodes occurred after 30 min annealing at 550 degrees C, presumably due to Al diffusion along the grain boundary of sputter-W film. For the CVD-W contacted junction diodes, insertion of a thin TiN barrier layer between the Al and W film was effective in suppressing the formation of WAl12 and thus improved the device's thermal stability.
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    Chemical mechanical polishing for selective CVD-W
    (1997-10-30)
    Wang, MT
    ;
    Yeh, WK
    ;
    Tsai, MS
    ;
    Tseng, WT
    ;
    Chang, TC
    This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
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    Formation of Cr-O and Cr-N-O films serving as Cu oxidation resistant layers and their N-2 pre-sintering effect
    (1998-12-14)
    Chuang, JC
    ;
    Chen, MC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This study investigates the Cu oxidation resistant layers of sputter deposited Cr-O and reactively sputter deposited Cr-N-O of 200 Angstrom thickness. with and without, thermal N-2 pre-sintering treatment. The resistance against Cu oxidation (or the highest annealing temperatures without causing Cu oxidation) of the Cr-O and Cr-N-O covered Cu films were found to be 350 and 500 degrees C, respectively, in an O-2 ambient. The inherent defects in the Cr-O lavers and the nitrogen doping in the Cr-N-O layers were believed to be the principal causes for the distinction of the resistance against Cu oxidation. With Na pre-sintering treatments on the Cr-O or Cr-N-O covered Cu films, the ability of resistance against Cu oxidation was degraded. The higher the N-2 pre-sintering temperature was, the lower the oxidation temperature of Cu became. The N-2 pre-sintering thermal process led to formation of defects on the Cr-O and Cr-N-O layers, resulting in the degradation of the ability of resistance against Cu oxidation. Thus, the application of Cr-O or Cr-N-O as a resistant layer against Cu oxidation should avoid such an excess thermal treatment. (C) 1998 Elsevier Science S.A. All rights reserved.
  • Thumbnail Image
    Item type:Item,
    Chemical mechanical polishing for selective CVD-W
    Wang, MT
    ;
    Yeh, WK
    ;
    Tsai, MS
    ;
    Tseng, WT
    ;
    Chang, TC
    This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
  • Thumbnail Image
    Item type:Item,
    Chemical mechanical polishing for selective CVD-W
    Wang, MT
    ;
    Yeh, WK
    ;
    Tsai, MS
    ;
    Tseng, WT
    ;
    Chang, TC
    This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.