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Now showing 1 - 10 of 32

A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
(2019-08-01)
Lee, Yuan-Sheng
;
Ho, Wei-Hsiang
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 2(31)-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm(2). The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.
A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
(2019-08-01)
Lee, Yuan-Sheng
;
Ho, Wei-Hsiang
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 231-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm2. The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.
A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking
(2018-01-01)
Hung, Chia-Tse
;
Huang, Yu-Ping
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 40 Gbh PAM-4 receiver comprised of continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 m1V at 40 Gb/s operation. Core area is 0.274mm(2).
A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery
(2018-01-01)
Lee, Yuan-Sheng
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A single chip optical receiver comprising of a font-end amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 2(31)-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10(-12) (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm(2). It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.
A 0.4V 53dB SNDR 250 MS/s Time-Based CT Delta Sigma Analog to Digital Converter
(2015-01-01)
Chen, Hung-Kai
;
Chen, Wei-Zen
;
Ren Zhiyuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of an ultra-low voltage (ULV), time-based, continuous-time Delta Sigma analog-to-digital data converter. By replacing the 2nd stage integrator with frequency-calibrated voltage bootstrapping VCO, it circumvents ULV design challenges while achieving a signal bandwidth up to 2 MHz. Back-gate adder, voltage amplifier, and bootstrapping logic cells are also proposed to enable 250 MHz sampling rate operation. The measured peak SNDR is 53 dB under a supply voltage of 0.4 V. The whole ADC consumes 526 mu W. Fabricated in a 90 nm CMOS process, the core area is 0.08 mm(2).
Distortion-characteristic estimation predistorter for high efficiency power amplifiers
(2016-12-01)
Ren, Zhiyuan
;
Chen, Hsiao-Hwa
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Power amplifier (PA) is one of important components in wireless communication system. However, its non-linear and memory characteristic cause harmful distortion, which significantly decreases the power efficiency and wastes electronic energy since the power of PA needs back off. To overcome the non-linear and memory problems, a novel method based on distortion-characteristic estimation algorithm is developed in this study. The main innovation of this study is manifested in two aspects: first, the authors use well designed training signals to estimate the distortion characteristic of the PA; second, a novel PA characteristic estimation algorithm is developed in order to calculate the optimal state of the ideal predistorter that behaves like the inverse characteristic of PA theoretically. Since this novel method does not require the error between original signals and feedback signals, it can avoid the significant errors caused by the time mismatch between source signals and feedback signals, and can increase the power efficiency of the PA. The simulation results validate the performance increase and the synchronisation-error immunity over the existing simplified filter look up table method.
A 25 Gb/s 1.13 pJ/b-10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS
(2017-03-01)
Huang, Shih-Hao
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time-interleaved integrating-type optical receiver, it provides 1:2 demultiplexing operation with a tolerance to lower bandwidth photodiodes. The bandwidth of current amplifier is chosen as 0.35x operating data rate for maximizing the receiver signal-to-noise ratio. Experimental results show that the receiver can achieve 25 Gb/s operation when integrated with a 9 or 17 GHz GaAs photodiode. Input sensitivities in the two cases are -7.2 dBm (w/i a 9 GHz photodiode) and -10.8 dBm (w/i a 17 GHz photodiode), respectively, for a bit error rate of less than 10(-12). In addition, a single-tap decision-feedback equalizer (DFE) is embedded to compensate photodiode bandwidth and improve input sensitivity. Integrated with a low-cost 9 GHz photodiode, the input sensitivity and timing margin of the receiver are improved by 2 dB and 0.25 UI, respectively, after DFE compensation. By utilizing a current integrator and time-interleaved comparators, its energy efficiency is 1.13 pJ/b at 25 Gb/s under a 1.2 V power supply. Fabricated in a 40 nm bulk-CMOS technology, the core circuit occupies a chip area of 0.007 mm(2) only.
A 2 x 20-Gb/s, 1.2-pJ/bit, Time-Interleaved Optical Receiver in 40-nm CMOS
(2014)
Huang, Shih-Hao
;
Hung, Zheng-Hao
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes a single-chip, 2 x 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1: 4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 mu A(pp) at bit-error-rate of less than 10(-12). Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm(2).
A 3.12 pJ/bit, 19-27 Gbps Receiver with 2 Tap-DFE Embedded Clock and Data Recovery
(2014)
Hong, Zheng-Hao
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm(2) only.
A Delta Sigma TDC with Sub-ps Resolution for PLL Built-in Phase Noise Measurement
(2016)
Chen, Wei-Zen
;
Kuo, Po-I
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A sub-ps Delta Sigma TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and Delta Sigma TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm(2).

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