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Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants
(2010-04-01)
Lee, Kuo-Fu
;
Li, Yiming
;
Hwang, Chih-Hong
;
電子工程學系及電子研究所
;
電信工程研究所
Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.
Asymmetric Gate Capacitance and High Frequency Characteristic Fluctuations in 16 nm Bulk MOSFETs Due to Random Distribution of Discrete Dopants
(2008)
Li, Yiming
;
Hwang, Chih-Hong
;
Yeh, Ta-Ching
;
電信工程研究所
;
Institute of Communications Engineering
Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits
(2009)
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Han, Ming-Hung
;
Lee, Kuo-Fu
;
Cheng, Hui-Wen
This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.
Propagation Delay Dependence on Channel Fins and Geometry Aspect Ratio of 16-nm Multi-Gate MOSFET Inverter
(2009)
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
Fin-type vertical channel Field Effect Transistors (FETs) are promising alternatives for the sub-32-nm CMOS technologies. This work investigates the impact of fin number and structure on V,h degradation and transient behavior of devices and circuits. Vertical channel transistors with different fin aspect ratio (AR = the fin height / the effective fin width) are explored. The multi-fin FinFETs (AR = 2) has a better channel controllability and a larger device width than tri-gate (AR = 1) and quasi-planar (AR = 0.5) MOSFETs. Though the increase of fin aspect ratio provides larger effective device width and driving current, the gate capacitance is increased also and limits the intrinsic device gate delay. The transient characteristics of single-/multi-fin inverter circuits are then examined by adding the load capacitance of circuits (1 and 10 fF). The added capacitance dominates the overall load capacitance and reduces the impact of the device intrinsic capacitance. The delay time is therefore dominated by the driving current of transistor and the multi-fin circuits performed a smaller delay time than the single-fin circuits. Additionally, the large driving capability of FinFET implies the less impact of load capacitance variation resulted from process variation. The multi-fin FinFETs exhibit better channel controllability against intrinsic parameter variation of active transistor and also mitigate the impact of process variation induced load capacitance variation of interconnect.
Electrical Characteristics of Nanoscale Multi-Fin Field Effect Transistors with Different Fin Aspect Ratio
(2009)
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
Device characteristics of multiple-fin silicon field effect transistors (FETs) arc sensitive to the channel fin aspect ratio (AR = the fin height / the fin width). In this study, dependence of characteristics on AR for single- and multi-fin FETs arc examined by using a three-dimensional device simulation. The threshold voltage (V(th)) variation of triplefin FET is smaller than that of singlc-fin one clue to a relatively larger effective device width. The triple-fin device with FinFET structure (AR = 2) exhibit rather stable V(th) roll-off characteristics owing to more uniform potential distribution inside the channel. The results of our study show that the driving current, transconductance, gate capacitance of FinFETs are superior to that of tri-gate (AR = 1) and quasi-planar (AR = 0.5) FETs. From the, layout viewpoint, FinFETs has the best layout area efficiency; consequently, to design a device with the subthreshold swing < 70 mV/dec, the layout area of FinFETs is L67 and 1.33 times smaller than those of quasi-planar and tri-gate FETs.
Characteristics Variability of Novel Lateral Asymmetry Nano-MOSFETs due to Random Discrete Dopant
(2009)
Lee, Kou-Fu
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Li, Yiming
;
電信工程研究所
In nanoscale silicon FETs, the lateral asymmetric channel (LAC) devices with higher channel doping concentration near the source-end have shown better control of the short channel effects. However, such asymmetric doping profile may introduce different fluctuations in device characteristics. In this paper, the asymmetric sketch of random dopants distribution near source and drain sides in 16 nm bulk MOSFETs' channel is explored. Discrete dopants distributed near-source end and near-drain end of channel region induce rather different fluctuations of gate capacitance and high frequency characteristics. The proposed inverse lateral asymmetry doping profile can effectively suppress both the DC and high frequency characteristic fluctuations, which may benefit the design of sub-20-nm MOSFETs.
Process- and Random-Dopant-Induced Characteristic Variability of SRAM with nano-CMOS and Bulk FinFET Devices
(2009)
Li, Tien-Yeh
;
Hwang, Chih-Hong
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this study, a three-dimensional "atomistic" circuit-device coupled simulation approach is advanced to investigate the process-variation and random dopant induced characteristic fluctuations in planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, the SNM fluctuation increases from 4% to 27%. To reduce the device variability induced fluctuation in circuit, a 16-nm-gate silicon-on-insulator fin-type field-effect-transistor (FinFET) with aspect ratio (fin height / fin width) equal to two is investigated. Due to its superior electrostatic integrity and larger effective device width, the fluctuation of SNM of 16-nm-gate FinFET SRAM could be suppressed by five times. Comparing with the 65 nm planar MOSFET SRAM, FinFETs' SRAM is promising in aggressively scaled silicon technology.
Effect of Flash Lamp Annealing and Laser Spike Annealing on Random Dopant Fluctuation of 15-nm Metal-Oxide-Semiconductor Devices
(2012-03-01)
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Chao, Ko-An
;
Li, Yiming
;
材料科學與工程學系
Comparison of two different implantation processing techniques for random dopant (RD)-induced threshold voltage fluctuation (sigma V-th) in 15-nm metal-oxide-semiconductor (MOS) devices is reported. Implantations of flash lamp annealing and laser spike annealing are simulated using a kinetic Monte Carlo (KMC) technique. The KMC generated distributions are mapped into device channel for three-dimensional quantum mechanical transport simulation to estimate threshold voltage fluctuation. The main results of this study show that the laser spike annealing could achieve 30% reduction of RDF-induced sigma V-th for low-power application of 15-nm MOS devices, compared with flash lamp annealing.
Effect of Process Variation on 15-nm-Gate Stacked Multichannel Surrounding-Gate Field Effect Transistor
(2009)
Han, Ming-Hung
;
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Li, Yiming
;
傳播研究所
Stacked multichannel transistor architectures were proposed recently which possess very attractive electrical characteristics on low leakage current and high driving current per layout area. However, due to complex manufacturing process, the process variation effect is inevitable and whose impact is unknown. Therefore, this study investigates the impact of process variation on 15-nm-gate stacked multichannel transistors consisting of the gate length deviation, channel position variation, quadruple-shaped channel structure and elliptic gate oxide. Our preliminary result shows that the stacked multichannel devices have good immunity to the gate length deviation and channel spacing variations; however, they are sensitive to the gate coverage ratio and gate oxide thickness variations. This study provides an insight into the device characteristic variations, which may benefit the development of nanoscale stacked multichannel transistors and circuits.
Discrete Dopant Induced Electrical and Thermal Fluctuation in Nanoscale SOI FinFET
(2007)
Li, Yiming
;
Hwang, Chih-Hong
;
Yu, Shao-Ming
;
Huang, Hsuan-Ming
;
電信工程研究所
The International Roadmap for Semiconductors has forecasted a transition from conventional bulk device to silicon-on-insulator (SOI) one, and then to multiple-gate SOI for high-performance devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, the discrete dopant induced electrical and thermal fluctuation of 16nm SOI FinFETs is for the first time explored. A three-dimensional atomistic" device simulation with quantum hydrodynamic equation is proposed and performed for electrical and thermal characteristics of the discrete dopant fluctuated SOI FinFETs. Discrete dopants are statistically positioned in the 3D channel region to study associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Effect of the discrete-dopant-number- and discrete-dopant-position-induced fluctuations on device characteristic including variations of the lattice and electron temperatures are advanced. The large-scale computational statistics study provides us an insight into the fluctuation of electrical and thermal characteristics and mechanism of immunity against fluctuation in SOI FinFETs.

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