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RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process
(2020-07-01)
Wu, Wei-Min
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Ker, Ming-Dou
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Chen, Shih-Hung
;
Chen, Jie-Ting
;
Linten, Dimitri
In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.
On-Chip Over-Voltage Protection Design Against Surge Events on the CC Pin of USB Type-C Interface
(2020-07-01)
Ke, Chao-Yang
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As fast charging being a comprehensive application in universal serial bus (USB) type-C products, the high-power delivery may cause the USB type-C interface in the high risk of surge events. Therefore, a switch realized by high voltage N-type metal oxide semiconductor transistor (HVNMOS) has been added to the configuration channel (CC) pin to prevent the internal circuits from surge damage. However, hot carrier degradation (HCD) on the HVNMOS was induced by surge events, especially when the HVNMOS was operating in the ON-state. To mitigate HCD on the HVNMOS switch during surge events, a new over-voltage protection (OVP) design with selected voltage-level detection was proposed and verified in a 0.15-mu m BCD technology. The proposed OVP circuit with a positive feedback is designed to turn off the gate of the HVNMOS switch for a longer time when surge zapping on the CC pin. The experimental results from silicon chip have successfully verified the proposed OVP structure in device level and circuit level, respectively.
Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High-Speed Digital Application in 16-nm FinFET Process
(2020-07-01)
Chang, Rong-Kun
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The FinFET architecture has widely been used in the digital circuit application, due to the good short channel effect control and driving current boost. However, the worse thermal dispassion and smaller effective silicon volume would cause the significant impacts during the circuits under electrostatic discharge (ESD) event. Thus, the ESD protection device should be installed into the high-speed digital circuit to enhance the ESD robustness. To avoid the effect of circuit performance, the parasitic capacitance of ESD device must be as low as possible. In this article, two types of Fin-diode-triggered rotated silicon-controlled rectifier (SCR) with dual ESD current path have been proposed and verified in a 16-nm FinFET CMOS process. The proposed devices have better current-handling capability, sufficiently low parasitic, compact layout area, and low leakage current.
A 13.56 MHZ METAMATERIAL FOR THE WIRELESS POWER TRANSMISSION ENHANCEMENT IN IMPLANTABLE BIOMEDICAL DEVICES
(2019-01-01)
Chen, Kuan-Jung
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Chen, Wei-Ming
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Tan, Li-Yang
;
Cheng, Yu-Ting
;
Ker, Ming-Dou
This paper presents a 13.56MHz metamaterial for wireless power transmission (WPT) enhancement in implantable biomedical devices based on the evanescent wave coupling mechanism. The power transmission efficiency (PTE) will increase from 46 to 51% with the metamaterial while the transmitting and receiving antennas are placed with a 1 cm distance and lcm offset horizontal misalignment, will increase from 39 to 46% with the metamaterial while the two antenna planes are placed at a distance of 1.5 cm with an axial offset of 15, and will increase from 28 to 50% with two pieces of metamaterial placed with a 0.5cm distance while the two antenna planes are placed with a 1.5 cm distance and 1 cm offset horizontal misalignment.
Energy Transformation Between the Inductor and the Power Transistor for the Unclamped Inductive Switching (UIS) Test
(2020-06-01)
Nidhi, Karuna
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Lee, Jian-Hsing
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Huang, Shao-Chang
;
Ker, Ming-Dou
;
交大名義發表
The fundamental model of energy transformation between the inductor and the power transistor for the unclamped inductive switching (UIS) test is inspected. Based on the experimental results, the energy stored in the inductor at the period of the channel turn-on can be dissipated by the power transistor after the channel is turned off. In this work, a new theoretical model to well describe the electrical and thermal behaviors of the power transistor during the unclamped inductive switching (UIS) test has been identified and analyzed with the experimental silicon results under different inductor values in 0.15 mu m BCD process. The total UIS energy reduced due to series resistance of the inductor and the power transistor has been theoretically explained and well matches with the experimental measured results on silicon.
Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes
(2020-01-01)
Chang, Rong-Kun
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In the implanted biomedical devices, the silicon chips with monopolar stimulation design have been widely applied. To protect the negative-voltage pins of the implanted silicon chip from the electrostatic discharge (ESD) damage, the ESD protection circuit should be carefully designed to avoid any wrong current path under normal circuit operation with the negative voltage. In this article, a new power-rail ESD clamp circuit for the application with an operating voltage of -6 V has been proposed and verified in a 0.18- $\mu \text{m}$ 3.3-V CMOS process. The proposed circuit, realized with only 3.3-V nMOS/pMOS devices, is able to prevent the gate-oxide reliability issue under this -6-V application. With the proposed ESD detection circuit, the turn-on speed of the main ESD clamp device, which is a stacked-nMOS (STnMOS), can be greatly enhanced. The STnMOS with a width of $400\mu \text{m}$ can sustain over 8-kV human body model (HBM) ESD stress and perform low standby leakage current of 5.4 nA at room temperature under the circuit operating condition with -6-V supply voltage.
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem
(2019-11-01)
Qian, Xin-Hong
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Wu, Yi-Chung
;
Yang, Tzu-Yi
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Cheng, Cheng-Hsiang
;
Chu, Hsing-Chien
Objective: To develop and verify a CMOS bone-guided cochlear implant (BGCI) microsystem with electrodes placed on the bone surface of the cochlea and the outside of round window for treating high-frequency hearing loss. Methods: The BGCI microsystem consists of an external unit and an implanted unit. The external system-on-chip is designed to process acoustic signals through an acquisition circuit and an acoustic DSP processor to generate stimulation patterns and commands that are transmitted to the implanted unit through a 13.56 MHz wireless power and bidirectional data telemetry. In the wireless power telemetry, a voltage doubler/tripler (2X/3X) active rectifier is used to enhance the power conversion efficiency and generate 2 and 3 V output voltages. In the wireless data telemetry, phase-locked loop based binary phase-shift keying and load-shift keying modulators/demodulators are adopted for the downlink and uplink data through high-Q coils, respectively. The implanted chip with four-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 mu A. Results: Electrical tests on the fabricated BGCI microsystem have been performed to verify the chip functions. The in vivo animal tests in guinea pigs have shown the evoked third wave of electrically evoked auditory brainstem response waveforms. It is verified that auditory nerves can be successfully stimulated and acoustic hearing can be partially preserved. Conclusion and Significance: Different from traditional cochlear implants, the proposed BGCI microsystem is less invasive, preserves partially acoustic hearing, and provides an effective alternative for treating high-frequency hearing loss.
On-chip Transient Detection Circuit for Microelectronic Systems against Electrical Transient Disturbances due to ESD Events
(2018-01-01)
Chen, Wen-Chieh
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new on-chip transient detection circuit which can detect electrical disturbances of system-level electrostatic discharge (ESD) is proposed. The circuit is designed with reduced physical area by utilizing dual-latched structure. With hardware/firmware co-design method, auto-recovery procedure can be activated by the detection circuit when microelectronic systems suffer system-level ESD events. The immunity level of microelectronic products against the electromagnetic interference (EMI) of ESD events can be effectively improved. The proposed on-chip transient detection circuit has been verified in a 0.18-mu m CMOS process with 1.8-V devices under system-level ESD tests.
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications
(2019-01-01)
Hung, Tao-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-mu m CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the posith e-to-V-ss stress and 5 kV under the negative-to-V-ss stress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented.
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process
(2019-09-01)
Luo, Zhicong
;
Yu, Li-Chin
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A wide-output, power-efficient, high-voltage charge pump with a variable number of stages is proposed and realized in a 0.18 mu m 1.8 V/3.3 V CMOS process. The proposed stage selection circuit changes the node voltages in the charge pump circuit in a domino effect to ensure that the maximum voltages across the terminals of each transistor are kept within the normal supply voltage (V-DD). The stage selection circuit is able to bypass or activate each stage of the charge pump. Experimental results indicate that the proposed charge pump provides a wide-output voltage range: 3.3-12.6 V from a 3.3 V input source. A peak efficiency of 70% was reached in the charge pump at a current loading of 3.5 mA. By selecting the optimal number of active stages, the overall power efficiencies can be greater than 60% under the output voltages of 4.8 V, 8.1 V, and 10.8 V, respectively. By optimizing the number of active stages, an increase of up to 35% power efficiency can be gained. The proposed stage selection circuit is applicable to other on-chip wide-output charge-pumps.

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