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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

Access type: Metadata onlyAuthor: search.filters.author.Li, Tien-Yeh

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Now showing 1 - 5 of 5
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    Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits
    (2009)
    Hwang, Chih-Hong
    ;
    Li, Tien-Yeh
    ;
    Han, Ming-Hung
    ;
    Lee, Kuo-Fu
    ;
    Cheng, Hui-Wen
    This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.
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    Characteristics Variability of Novel Lateral Asymmetry Nano-MOSFETs due to Random Discrete Dopant
    (2009)
    Lee, Kou-Fu
    ;
    Hwang, Chih-Hong
    ;
    Li, Tien-Yeh
    ;
    Li, Yiming
    ;
    電信工程研究所
    In nanoscale silicon FETs, the lateral asymmetric channel (LAC) devices with higher channel doping concentration near the source-end have shown better control of the short channel effects. However, such asymmetric doping profile may introduce different fluctuations in device characteristics. In this paper, the asymmetric sketch of random dopants distribution near source and drain sides in 16 nm bulk MOSFETs' channel is explored. Discrete dopants distributed near-source end and near-drain end of channel region induce rather different fluctuations of gate capacitance and high frequency characteristics. The proposed inverse lateral asymmetry doping profile can effectively suppress both the DC and high frequency characteristic fluctuations, which may benefit the design of sub-20-nm MOSFETs.
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    Process- and Random-Dopant-Induced Characteristic Variability of SRAM with nano-CMOS and Bulk FinFET Devices
    (2009)
    Li, Tien-Yeh
    ;
    Hwang, Chih-Hong
    ;
    Li, Yiming
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    In this study, a three-dimensional "atomistic" circuit-device coupled simulation approach is advanced to investigate the process-variation and random dopant induced characteristic fluctuations in planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, the SNM fluctuation increases from 4% to 27%. To reduce the device variability induced fluctuation in circuit, a 16-nm-gate silicon-on-insulator fin-type field-effect-transistor (FinFET) with aspect ratio (fin height / fin width) equal to two is investigated. Due to its superior electrostatic integrity and larger effective device width, the fluctuation of SNM of 16-nm-gate FinFET SRAM could be suppressed by five times. Comparing with the 65 nm planar MOSFET SRAM, FinFETs' SRAM is promising in aggressively scaled silicon technology.
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    Reduction of Discrete-Dopant-Induced High-Frequency Characteristic Fluctuations in Nanoscale CMOS Circuit
    (2008)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yeh, Ta-Ching
    ;
    Huang, Hsuan-Ming
    ;
    Li, Tien-Yeh
    As the dimension of semiconductor device shrunk into nanoscale, characteristic fluctuation is more pronounced, and become crucial for circuit design. Diverse approaches have been reported to investigate and suppress the random-dopant-induced fluctuations in devices. However, attention is seldom drawn to the existence of high-frequency characteristic fluctuations of active device. In this paper, intrinsic high-frequency characteristic fluctuations of the nanoscale MOSFET circuit induced by random dopants are intensively explored using an experimentally validated simulation methodology, where fluctuation suppression technique is further examined. The circuit gain, the 3db bandwidth and the unity-gain bandwidth of the tested circuit are estimated concurrently capturing the discrete-dopant-number-and discrete-dopant-position-induced fluctuations. This study provides an insight into discrete-dopant-induced intrinsic high-frequency characteristic fluctuations and examines the potential fluctuation suppression technique for nanoscale transistor circuit.
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    Comprehensive Examination of Threshold Voltage Fluctuations in Nanoscale Planar MOSFET and Bulk FinFET Devices
    (2008)
    Hwang, Chih-Hong
    ;
    Cheng, Hui-Wen
    ;
    Yeh, Ta-Ching
    ;
    Li, Tien-Yeh
    ;
    Huang, Hsuan-Ming
    Intrinsic fluctuations on device characteristics, such as the threshold voltage (V(th)) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced Vth fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO(2) for the 1.2 and 0.8 nm EOTs, Al(2)O(3) for the 0.4 nm EOT and HfO(2) for the 0.2 nm EOT) are then for the first time compared with the results of 16nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property. Result of this study confirms the suppression of Vth fluctuations with the gate oxide thickness scaling (using high-kappa dielectric). It's found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device's scaling and have potential in the nanoelectronics application.