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Hot-Carrier Injection-Induced Disturb and Improvement Methods in 3D NAND Flash Memory
(2019-01-01)
Lin, Wei-Liang
;
Tsai, Wen-Jer
;
Cheng, C. C.
;
Lu, Chun-Chang
;
Ku, S. H.
We investigate a hot-carrier injection- induced program disturb in a 3D NAND flash memory. As there exist specific coding patterns, a "down-coupling" region and a "pre-charge" regions are formed during program-verify and the following program phases, respectively, in the inhibit cell strings. A high heating field is built nearby the PGM wordline. Hot carriers may inject into the inhibit cells as Vpgm is applied. Soft ramp-down and pre-turn-on schemes are proposed to mitigate this disturb.
Investigation of Electron and Hole Lateral Migration in Silicon Nitride and Data Pattern Effects on ${V}_{{t}}$ Retention Loss in a Multilevel Charge Trap Flash Memory
(2019-12-01)
Liu, Yu-Heng
;
Zhan, Ting-Chien
;
Wang, Tahui
;
Tsai, Wen-Jer
;
Lu, Tao-Cheng
We investigate electron and hole lateral migration in retention loss in a multilevel charge trap flash memory. We use hot electron program and band-to-band tunneling hot hole erase to inject various amounts of electrons and holes at the two ends of a SONOS cell. A random telegraph signal (RTS) method is used to distinguish electron and hole lateral movements in silicon nitride. In retention measurement, we apply a voltage to the gate or the source/drain to enhance or retard trapped charge vertical loss and lateral migration. From the evolution characteristics of RTS and traces in retention, we are able to identify the separate roles of electron vertical loss, electron lateral migration, and hole lateral migration in different data patterns. Due to the interaction of stored electrons and holes, we find that retention loss in a program state exhibits a turnaround characteristic as program level increases. loss at low program levels is attributed to hole lateral migration from a neighboring bit. At higher program levels, the influence of hole lateral migration is reduced and loss is dominated by electron vertical loss and lateral migration.
Investigation of Data Pattern Effects on Nitride Charge Lateral Migration in a Charge Trap Flash Memory by Using a Random Telegraph Signal Method
(2018-01-01)
Liu, Y. H.
;
Lin, H. Y.
;
Jiang, C. M.
;
Wang, Tahui
;
Tsai, W. J.
Data pattern effects on nitride charge lateral migration and V-t retention loss in a charge trap flash memory is investigated. We use channel hot electron program and band-to-band tunneling hot hole erase to inject different amounts of electrons and holes at the two sides of a channel in a SONOS cell. An interface oxide trap near an injected charge packet and its associated random telegraph signal (RTS) are used as an internal probe to detect a local channel potential change resulting from trapped charge lateral migration. Vt retention loss and RTS in various charge storage patterns are characterized and analyzed. At a similar built-in electric field, nitride trapped holes are found to be more mobile than trapped electrons in lateral migration.
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
;
Ku, S. H.
;
Cheng, C. H.
;
Lee, C. W.
;
Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell String
(2019-04-01)
Lin, Wei-Liang
;
Tsai, Wen-Jer
;
Cheng, C. C.
;
Ku, S. H.
;
Liu, Lenvis
Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 mu s or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in "pseudo" charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
(2018-01-01)
Ku, S. H.
;
Lin, T. W.
;
Cheng, C. H.
;
Lee, C. W.
;
Chen, Ti-Wen
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR(2 )is also evaluated.
Study of Thyristor-Mode Dual-Channel NAND Flash Devices
(2018-01-01)
Lo, Roger
;
Lue, Hang-Ting
;
Chen, Weichen
;
Du, Pei-Ying
;
Hsu, Tzu-Hsuan
A novel dual-channel 3D NAND device was proposed previously [1]. In addition to the N- and P-channel read operations, such device can also perform a special "thyristor mode" which possesses super steep subthreshold slope (S.S. similar to 0). In this work, we studied 4 different types of read methods with the same device, which are normal N- and P-channel read, and thyristor-mode N- and P-channel read, respectively. These 4 different read methods can be carried out by just simply changing the bias arrangements of wordlines so that the IdVg curves can behave differently. An interesting finding is that the Vt window of PIE cycling and retention are quite different among these sensing methods. It may provide a new methodology to understand the charge storage mechanisms. 'this work provides a comprehensive study for understanding the operation physics of this novel device.
Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
(2018-01-01)
Lu, C. C.
;
Cheng, C. C.
;
Chiu, H. P.
;
Lin, W. L.
;
Chen, T. W.
Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.
Excellent High Temperature Retention of TiOXNV ReRAM by Interfacial Layer Engineering
(2018-01-01)
Lin, Yu-Hsuan
;
Lee, Dai-Ying
;
Wang, Chao-Hung
;
Lee, Ming-Hsiu
;
Ho, Yung-Han
Since the resistance switching of the transition metal oxide (TMO) resistive random access memory (ReRAM) is based on thc interaction between the oxygen ions and vacancies, the unintentional oxygen/vacancy reaction should be avoided during data retention. This work demonstrates significant improvements on the retention performance by inserting a Si layer in the TiO Ny ReRAM to block the diffusion of oxygen ions through the Ti/TiO,N interface. The mechanism and factors that influenced thc IIRS and LRS retention arc also studied. The retention performance of HRS is correlated with its RESET level while the LRS retention depends on the programming current. The proposed Ti/Si/TiO,N, ReRAMs can switch for more than 103 cycles from array testing results.
Variations of V-t Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
(2011-04-01)
Chou, Y. L.
;
Chung, Y. T.
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Wang, Tahui
;
Ku, S. H.
;
Zou, N. K.
Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V-t of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V-t) are characterized. We find the following: 1) The magnitude of Delta V-t exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V-t retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V-t and a tunneling front model to study the spread of a retention V-t distribution in a SONOS Flash memory.

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