<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

Filters

1997 - 199912000 - 20042

Settings

🏛️國立陽明交通大學機構典藏

Access type: Metadata onlyAuthor: search.filters.author.Wang, MF

Search Results

Now showing 1 - 3 of 3
  • Thumbnail Image
    Item type:Item,
    A model for photoresist-induced charging damage in ultra-thin gate oxides
    (1997)
    Lin, HC
    ;
    Chien, CH
    ;
    Wang, MF
    ;
    Huang, TY
    ;
    Chang, CY
    The role of photoresist (PR) in affecting the gate oxide damage during plasma processing boas reexamined in this work. if was observed that, during the O-2 plasma ashing, more severe antenna effect may occur in devices with PR covering. A model is proposed to explain this phenomenon. This model considers the ability of plasma current injection through the substrate contacts, which are hindered by PR covering, to adjust the potential difference between gate electrode and substrate. We Sound that the presence of PR, antenna ratio, and gate-oxide thickness are all important parameters for charging damage effect.
  • Thumbnail Image
    Item type:Item,
    Thermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistors
    (2001)
    Wang, MF
    ;
    Kao, YC
    ;
    Huang, TY
    ;
    Lin, HC
    ;
    Chang, CY
    The effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n(+)/p junctions need higher thermal budget than p(+)/n junctions to achieve low leakage performance. It was also found fron C-V measurements that the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. A hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel transistors.
  • Thumbnail Image
    Item type:Item,
    Effects of base oxide in HfSiO/SiO2 high-k gate stacks
    (2004)
    Wu, WH
    ;
    Chen, MC
    ;
    Wang, MF
    ;
    Hou, TH
    ;
    Yao, LG
    Electrical characteristics of HfSiO/SiO2 high-k gate stacks have been extensively explored with regard to the effects of base oxide. The flatband voltage shift in N/PMOS capacitors is independent of base oxide thickness, and the dielectric breakdown of the gate stacks is determined by base oxide. In addition, base oxide thickness has a great impact on device performance and charge trapping, presumably due to remote Coulomb scattering (RCS) in the HfSiO bulk layer and direct tunneling through the base oxide. Threshold voltage instability induced by charge trapping will be a major reliability concern for Hf-based high-k gate dielectrics in the future.