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Normally-Off Tri-Gate GaN MIS-HEMTs with 0.76 m Omega center dot cm(2) Specific On-Resistance for Power Device Applications
(2019-08-01)
Wu, Chia-Hsun
;
Chen, Jian-You
;
Han, Ping-Cheng
;
Lee, Ming-Wen
;
Yang, Kun-Sheng
A GaN metal-insulator-semiconductor high electronmobility transistor (MIS-HEMT) using tri-gate architecture and hybrid ferroelectric charge trap gate stack is demonstrated for normally-off operation. Compared with the conventional planar device, the tri-gate device has the 2-D electron gas (2-DEG) channel exposed on the nanowire sidewalls, so that the trapped charges in the HfON charge-trapping layer can easily deplete the channel from the sidewalls, leading to a high positive threshold voltage (V-th) to realize the normally-off operation. Moreover, through this electrostatic control on the sidewall, a high density of negative charge caused by hybrid ferroelectric charge trap gate stack with the optimized tri-gate structure, the tri-gate device can achieve normally-off GaN device with both low on-resistance (R-ON) and high positive V-th. The designed tri-gate device exhibits a high V-th of +2.61 V at current density (I-DS) = 1 mu A/mm, a high maximum current density (I-DS, MAX) of 896 mA/mm, a low R-ON of 5.0 Omega center dot mm and a high breakdown voltage (BV) of 788 V. To the best of our knowledge, the proposed tri-gate device shows the lowest specific on-resistance (R-ON,R- SP) among reported normallyoff GaN device results with BV > 650 V.
Growth Parameters Optimization of GaN High Electron Mobility Transistor Structure on Silicon Carbide Substrate
(2014-01-01)
Wong, Y. Y.
;
Huang, S. C.
;
Huang, W. C.
;
Lumbantoruan, F.
;
Chiu, Y. S.
High electron mobility transistors heterostructures of AlGaN/GaN were grown by metalorganic chemical vapor deposition system on silicon carbide substrate. The growth parameters such as AlN buffer thickness, AlN spacer growth time and Al content in AlGaN barrier layer were optimized. Moreover, the effects of chamber pressure and V/III ratio at the initial growth state of GaN on film crystal quality were also investigated. The optimized AlGaN/GaN heterostructure has AlN buffer thickness of 120 nm, AlN spacer growth time of 10 s and Al content of 28% in the barrier layer. Furthermore, as a result of using higher chamber pressure and lower V/III, both the GaN crystal quality and electron mobility in the AlGaN/GaN were also significantly improved. After the growth parameter optimization, the GaN (002) and (102) planes exhibited X-ray rocking curve widths of 209 arcsec and 273 arcsec, respectively. Besides, the AlGaN/GaN structure also has an electron mobility of 1832 cm(2)/V-s and a sheet electron density of 1.08 10(13) cm(-2), which yielding a sheet resistance of 316 Omega/sq.
Effect of AlN Spacer on the AlGaN/GaN HEMT Device Performance at Millimeter-wave Frequencies
(2018-01-01)
Wang, Chun
;
Hsu, Heng-Tung
;
Huang, Ting-Jui
;
Fan, Jun-Kai
;
Chang, Edward Yi
The effect of the AlN spacer on the performance of AlGaN/GaN HEMT devices at 38 GHz is experimentally investigated. The measurement results revealed that the device with spacer showed superior performance in terms of the maximum drain current. RF wise, substantial improvement in the cut-off frequency and the maximum oscillation frequency was also observed for devices with spacer. A saturated output power density of 4.21 W/mm with 35.02% power-added efficiency (PAE) at 38 GHz were achieved for device with 70nm gate length.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect
(2014-07-01)
Tsai, Szu-Ping
;
Hsu, Heng-Tung
;
Chiang, Che-Yang
;
Tu, Yung-Yi
;
Chang, Chia-Hua
We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.
Normally-OFF GaN MIS-HEMT With F- Doped Gate Insulator Using Standard Ion Implantation
(2018-01-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Quang Ho Luc
;
Hsu, Ching-Yi
;
Hsieh, Ting-En
A normally-OFF GaN metal-insulator-gate high electron mobility transistors with fluorine doped gate insulator has been fabricated using standard ion implantation technique. Fluorine ions with negative charges were doped lightly into both the gate insulator and the partially recessed barrier layer, resulting in high positive threshold voltage (V-th) for the device, meanwhile preserving low ON-resistance. Compared to the fluorine-free and recess-free device, only about 16% increase of ON-resistance was observed for the F- doped devices. The fabricated F- doped device exhibits a threshold voltage of +0.68 V at I-Ds = 5 mu A/mm, a current density of 620 mA/mm, an OFF-state breakdown voltage of 800 V, and high ON/OFF current ratio of 10(10). For thermal stability consideration of fluorine dopant, the V-th-thermal stability test and positive bias temperature instability test were also discussed.
High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications
(2018-07-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Liu, Shih-Chien
;
Hsieh, Ting-En
;
Lumbantoruan, Franky Juanda
A GaN metal-insulator-semiconductor-high electron mobility transistor (HEMT) using hybrid ferroelectric charge trap gate stack (FEG-HEMT) is demonstrated for normally-OFF operation. The ferroelectric (FE) polarization increases the number of trapped charges in the HfON charge trapping layer, leading to high positive threshold voltage (V-th) shift for the normally-OFF device. Besides, under the positive bias temperature instability (PBTI) test, the internal electric field induced by FE polarization causes smoother slope of the conduction band in FE gate stack, resulting in better V-th stability. With the proposed hybrid FE charge trap gate stack, the device exhibits a high V-th of +2.71 V at I-DS = 1 mu A/mm, a high maximum current density of 820 mA/mm and low on-resistance (R-ON) of 11.1 Omega . mm. The FE device also shows good V-th-temperature stability compared to the non-FE device results. Besides, a high current device with 40 A is also fabricated in this letter to demonstrate the feasibility of the proposed FEG-HEMT device for high power device application.
AlGaN/GaN MIS-HEMTs With High Quality ALD-Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants
(2018-12-01)
Wang, Huan-Chung
;
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Luc, Quang Ho
;
Liu, Shih-Chien
We demonstrate the electrical performances of AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistors (MIS-HEMTs) with high quality Al2O3 gate dielectric deposited by plasma enhanced atomic layer deposition using both H2O and remote O-2 plasma as oxygen sources. Excellent gate-dielectric/GaN interface and Al2O3 film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS-HEMT device exhibited high on/off current ratio of similar to 10(10), steep subthreshold slope, small gate leakage current, low dynamic on-resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O-2 plasma in the ALD-Al2O3 deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS-HEMTs production.
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications
(2016-11)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
The electrical performances of gate-recessed AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using the damage-free neutral beam etching (NBE) method are demonstrated. The NBE method could eliminate the plasma-induced defects generated by irradiating ultraviolet/VUV photons in the conventional inductively coupled plasma reactive ion etching method. The AlGaN/GaN HEMT device fabricated using the new gate recess process exhibited superior electrical performances, including a maximum drain current density (I-DS,I-max) of 1.54 A/mm, low 1/f noise, a current-gain cutoff frequency (f(T)) of 153 GHz, a maximum frequency of oscillation (f(MAX)) of 167 GHz, and a minimum noise figure (NFmin) of 3.28 dB with an associated gain (G(AS)) of 5.06 dB at 54 GHz. Such superior characteristics confirm the inherent advantages of adopting the damage-free NBE process in fabricating GaN devices for millimeter-wave applications.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs by Strain Engineering Design
(2016-10)
Tsai, Szu-Ping
;
Hsu, Heng-Tung
;
Wuerfl, Joachim
;
Chang, Edward Yi
;
材料科學與工程學系
The piezoelectric polarization of the AlGaN/GaN high-electron-mobility transistors (HEMTs) is strongly related to the strain state in the active area. Therefore, understanding the strain behavior inside the channel is crucial to the device electrical performance improvement of devices. This paper, for the first time, reveals the potential of optimizing flip-chip structures with active-region bumps to modulate the strain state of the AlGaN/GaN HEMT for enhancing the piezoelectric effect. The thermo-mechanical strain is observed to be affected by the physical dimensions and the material properties of the package. Thus, incorporating device strain engineering into packaging design will be very important for GaN devices due to their strong piezoelectric effects.
Low Interface Trap Densities and Enhanced Performance of AlGaN/GaNMOS High-Electron Mobility Transistors Using Thermal Oxidized Y2O3 Interlayer
(2015-12-01)
Liao, Chongnan
;
Zou, Xuming
;
Huang, Chun-Wei
;
Wang, Jingli
;
Zhang, Kai
AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with Y2O3 interlayer have been investigated to improve the interface quality. With the HfO2/Y2O3 stack gate dielectrics, the devices show a saturated drain current density of up to similar to 943 mA/mm. Meanwhile, the pulsed I-d-V-g measurement indicates interface traps are as low as 5.2 x 10(11) cm(-2), and the pulsed-IV measurement exhibits great resistance to current collapse. Furthermore, the devices also present good reliability under negative bias stress. Therefore, the interface engineering based on Y2O3 has a potential to open up a new avenue to high-performance AlGaN/GaN MOS-HEMTs.

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