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A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
(2020-01-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.
Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O-3 Treatment
(2018-01-01)
Yeh, M. -S.
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Luo, G. -L.
;
Hou, F. -J.
;
Sung, P. -J.
;
Wang, C. -J.
Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ digital O-3 treatment in ALD chamber was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. The treatment effects were checked by AFM and C-V measurements. By combining this treatment with optimized microwave annealing, sub-threshold slope and the I-ON/I-OFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low V-D = 0.6 V was realized. Finally, simulations on an ideal Ge CMOS inverter were presented.
Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect
(2019-06-01)
Huang, Shih-En
;
Yu, Chien-Lin
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the fin-width (W-Fin) sensitivity of threshold voltage (V-T) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller VT sensitivity to W-Fin than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the V-T sensitivity to W-Fin for NC-FinFETs. Our study may provide insights for future scaling of FinFETs.
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
(2018-01-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This work examines the metal-ferroelectricinsulator-semiconductor (MFIS) negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. With the aid of a short-channel NC-FinFET compact model, we confirm the functionality and determine the standby-power/switching-energy/delay performance of logic circuits (5-stage inverter and 4-bit Manchester carry-chain (MCC) adder) employing 14nm ULP NC-FinFETs versus FinFETs. We show that the inverse V-ds-dependency of threshold voltage (V-T), also known as the negative DIBL, of NCFET is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTI.) circuits, especially for the PTI, at low V-DD.
RF Harvesting System for Low-Power Applications Using FinFETs
(2019-01-01)
Nagateja, T.
;
Srinivasulu, A.
;
Pal, Dipankar
;
交大名義發表
;
National Chiao Tung University
Two high efficiency FinFET-based negative voltage rectifiers for radio frequency (RF) applications have been proposed. These circuits have very good power conversion efficiency (PCE) especially in small RF input conditions. The designs are simple, yet the novelty lies in realization utilizing normal threshold voltage Si FinFET (NVT), low threshold voltage Si FinFET (LVT), high threshold voltage Si FinFET (HVT) which offers power efficient solutions for RF-harvesting applications. Simulations are carried out on 20 nm FinFET model files employing Cadence software. Performance comparisons of these three models have been done to validate the two-designs and to benchmark them. We have investigated how to improve parameters such as the output DC voltage, output DC power and PCE of rectifier. With LVT FinFET the second rectifier proposed offers 92% of PCE, -342 mV of DC output voltage at RF input of 0.4 V at 915 MHz frequency which is the best performance.
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
(2019-04-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse V-ds-dependence of threshold voltage (V-T), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low V-DD.
Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations.
(2017-01-01)
Chang, Chia-Ning
;
Chen, Yin-Nien
;
Huang, Po-Tsang
;
Su, Pin
;
Chuang, Ching-Te
This paper investigates and evaluates analog and digital low-dropout linear voltage regulators (LDO) with FinFET, TFET and hybrid TFET-FinFET implementations. We utilize Sentaurus physics-based atomistic 3D TCAD mixed-mode simulations for device characteristics and HSPICE with look-up tables based on Verilog-A models calibrated with TCAD simulation results. Frequency response, load regulation and power supply rejection ratio (PSRR) are evaluated for analog LDOs under low, medium and high bias-current conditions. The results indicate that for analog implementations, TFET-LDO and hybrid-LDO provide better loop-gain and PSRR than FinFET-LDO under low and medium operating currents, whereas at higher operating current, FinFET implementation would outperform. As operating voltage is reduced, the performances of analog implementations degrade, and digital implementations become favorable for VIN below around 0.55V. We further show that for digital LDO, all FinFET implementation provides superior performance over all TFET and hybrid TFET-FinFET implementations.
Analog and RF Characteristics of Power FinFET Transistors With Different Drain-Extension Designs
(2018-10-01)
Chen, Bo-Yuan
;
Chen, Kun-Ming
;
Chiu, Chia-Sung
;
Huang, Guo-Wei
;
Chen, Hsiu-Chih
Analog and RF characteristics of power FinFET transistors with different drain-extension structures are investigated for microwave integrated circuit applications. The power FinFETs were designed based on the drain-extended MOSFET structure and fabricated using a standard low-voltage FinFET process. Three various drain-extension configurations are demonstrated and compared. With the low-doped drain extension, the breakdown voltage of power FinFETs is higher than 6.5 V for all samples. For standard power devices, where the drain extension is performed with narrow fins, a high drain resistance is inevitable, resulting in high on-resistance and poor analog and RF performances. For devices with wide drain-extension fins (wide drain FinFET) or a planar drain extension (hybrid FinFET), lower drain resistances are obtained owing to the larger extension width. Therefore, the on-resistances of the wide drain and hybrid devices are much lower than that of the standard counterpart. Moreover, these devices with modified drain extensions also exhibit better analog and RF behaviors. The cutoff frequency of power FinFETs is boosted from 30 to 53 GHz when the drain extension is changed from narrow fins to a planar layout. These experimental results indicate that RF power FinFETs with good performance would be realized with the modified drain-extension designs.
InGaAs Junctionless FinFETs With Self-Aligned Ni-InGaAs S/D
(2018-01-01)
Chang, Po-Chun
;
Hsiao, Chih-Jen
;
Lumbantoruan, Franky Juanda
;
Wu, Chia-Hsun
;
Lin, Yen-Ku
In this paper, the InGaAs junctionless (JL) FinFET with notable electrical performance is demonstrated. The device with W-fin down to 20 nm, EOT of 2.1 nm, and L-G = 60 nm shows high I-ON = 188 mu A/mu m at V-DD = 0.5 V and I-OFF = 100 nA/mu m, I-ON/I-OFF = 5 x 10(5), DIBL = 106 mV/V and SS = 96 mV/dec. The device also exhibits a decent extrinsic transconductance (G(m)) of 1142 mu S/mu m at V-DS of 0.5 V. This high performance is attributed to the moderate doping concentration to ensure the channel carriers could be effectively depleted and the low R-SD realized by self-aligned Ni-InGaAs alloy S/D. Furthermore, we also examine the temperature dependence of the main electrical parameters of the JL transistor.
An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET
(2018-01-01)
Hsieh, E. Ray
;
Jiang, Meng-Ru
;
Lin, Jian-Li
;
Chung, Steve S.
;
Chen, Tse Pu
In this paper, we have developed a methodology of a lateral profiling technique of the channel local temperature in 14 nm FinFET, incurred by the self-heating effect (SHE). As SHE happens, the thermal source generated near the drain will dissipate toward the source side. Since the interaction between RTN trap and channel carriers is very sensitive to the temperature, the channel local temperature can be extracted through this interaction process between random-telegraph-noise (RTN) trap and carriers, and the position of the channel local temperature can be obtained from the RTN trap position. The results show that the highest temperature happens at the drain edge during SHE and pFinFET exhibits a much higher temperature than that of nFinFET. Furthermore, the distribution of channel local temperature can be described by the Fourier's law of thermal conduction. Averaged channel temperature can be used to extract the thermal resistance, R-th, which increases rapidly as the channel length is scaled down to 20 nm, further degrading the SHE, in terms of a significant short channel effect. We also found that the incremental channel resistance is proportional to the incremental channel local temperature, whose slope indicates the degree of SHE, and the slope of pFinFET is larger than that of nFinFET. Finally, SHE will cause 10% and 14% degradation of IdVds for n- and pFinFET respectively. This can be reasonably explained by the decay of saturation velocity in high temperature. The results obtained based on this methodology will help us on the understanding of the SHE impact on a nano-scaled FinFET device.

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