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🏛️國立陽明交通大學機構典藏

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    Effect of thermal treatment on resistive switching characteristics in Pt/Ti/Al2O3/Pt devices
    (2008-12-25)
    Lin, Chih-Yang
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    Lee, Dai-Ying
    ;
    Wang, Sheng-Yi
    ;
    Lin, Chun-Chieh
    ;
    Tseng, Tseung-Yuen
    Resistive switching characteristics of Pt/Ti/Al2O3/Pt memory devices annealed at various temperatures including 400 degrees C, 500 degrees C and 600 degrees C for 1 h under ambient condition were investigated in the study. The Al2O3 thin films annealed at up to 600 degrees C for 1 h remain amorphous phase based on the X-ray diffraction (XRD) analyses. As increasing annealing temperature, the forming voltage (activating the pristine device) of the memory device decreases in contrast to the rising trend of the turn-on voltage (switching from high to low resistance state). However, the turn-off voltage (switching from low to high resistance state) is almost uninfluenced by thermal annealing. These phenomena might be attributed to the interdiffusion between Ti and Al2O3, based on the analyzed results of secondary ion mass spectroscopy (SIMS) and high resolution transmission electron microscope (HR-TEM). Moreover, the thermal annealing process eventually creates high conducting paths with a high density of oxygen vacancies between the two electrodes. (c) 2008 Elsevier B.V. All rights reserved.
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    Reproducible resistive switching behavior in sputtered CeO2 polycrystalline films
    (2008-12-25)
    Lin, Chih-Yang
    ;
    Lee, Dai-Ying
    ;
    Wang, Sheng-Yi
    ;
    Lin, Chun-Chieh
    ;
    Tseng, Tseung-Yuen
    Sputter-deposited CeO2 film in the metal-insulator-metal structure exhibits repeatable resistive switching behavior under voltage sweep. Based on the X-ray diffraction patterns and the cross-sectional scanning electron microscope image, the CeO2 film is polycrystalline with columnar grains perpendicular to the bottom electrode. Moreover, due to the symmetric device structure of Pt/CeO2/Pt, the resistive switching behavior is independent of bias polarity so that both positive and negative voltages can switch the device from high conducting state (ON-state) into low conducting state (OFF-state) and then back to ON-state, which is named non-polar resistive switching. The resistance ratio between two memory states is about five orders of magnitude, which is stable over 10(4) S at 0.3 V stress. in addition, the resistance ratio decreases with increasing the current compliance during forming process. The stability of ON-state, OFF-state, and as-deposited film state (the state before performing forming process) against temperature is also investigated in this study, showing that the OFF-state is less stable. (C) 2008 Elsevier B.V. All rights reserved.
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    Formation of the distributed NiSiGe nanocrystals nonvolatile memory formed by rapidly annealing in N-2 and O-2 ambient
    (2010-10-01)
    Hu, Chih-Wei
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    Chang, Ting-Chang
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    Tu, Chun-Hao
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    Chiang, Cheng-Neng
    ;
    Lin, Chao-Cheng
    In this work, electrical characteristics of the Ge-incorporated Nickel silicide (NiSiGe) nanocrystals memory device formed by the rapidly thermal annealing in N-2 and O-2 ambient have been studied. The trapping layer was deposited by co-sputtering the NiSi2 and Ge, simultaneously. Transmission electron microscope results indicate that the NiSiGe nanocrystals were formed obviously in both the samples. The memory devices show obvious charge-storage ability under capacitance-voltage measurement. However, it is found that the NiSiGe nanocrystals device formed by annealing in N-2 ambient has smaller memory window and better retention characteristics than in O-2 ambient. Then, related material analyses were used to confirm that the oxidized Ge elements affect the charge-storage sites and the electrical performance of the NCs memory. (C) 2010 Elsevier B.V. All rights reserved.
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    Resistive switching characteristics of Sm2O3 thin films for nonvolatile memory applications
    (2011-09-01)
    Huang, Sheng-Yao
    ;
    Chang, Ting-Chang
    ;
    Chen, Min-Chen
    ;
    Chen, Shih-Ching
    ;
    Lo, Hung-Ping
    This study investigates a sputtered Sm2O3 thin film to apply into a resistive random access memory device. The proposed device exhibits a stable resistance ratio of about 2.5 orders after 10(4) cycling bias pulses and no degradation for retention characteristics monitored after an endurance test at 85 degrees C. The conduction mechanisms for low and high resistance states are dominated by ohmic behavior and trapcontrolled space charge limited current, respectively. The resistance switching is ascribed to the formation/rupture of conductive filaments. (C) 2011 Elsevier Ltd. All rights reserved.
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    Improved resistive switching properties of Ti/ZrO2/Pt memory devices for RRAM application
    (2011-07-01)
    Wang, Sheng-Yu
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    Tsai, Chen-Han
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    Lee, Dai-Ying
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    Lin, Chih-Yang
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    Lin, Chun-Chieh
    In this study, we have investigated the effect of current compliance during forming process on resistive switching (RS) characteristics of the Ti/ZrO2/Pt device. The higher the current compliance is, the larger RS operation voltage is needed. The Ti/ZrO2/Pt device with high device yield can be operated over 10,000 RS cycles by sweeping dc voltage. and the on and off two memory states exhibit good stability under 0.3 V stress voltage. Moreover, the data retention of both memory states is over 10(5) s. As applying +6-V 10-ns and -3-V 10-ns voltage pulses on the device, there are operation errors observed during continuous write-read-erase-read cycles until increasing the pulse width to 50 ns. Nondestructive readout tests are also performed on the Ti/ZrO2/Pt device before and after 10(3) pulse cycles without any obvious degradation observed. Compared with reported ZrO2-based memory devices, our Ti/ZrO2/Pt device exhibits better RS properties and has a high potential for memory application. (C) 2011 Elsevier B.V. All rights reserved.
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    Mechanism and characterizations studies of resistive switching effects on a thin FeOx-transition layer of the Ti/TiN/SiO2/FeOx/FePt structure by thermal annealing treatments
    (2011-12-15)
    Chang, Yao-Feng
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    Feng, Li-Wei
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    Chang, Ting-Chang
    ;
    電子工程學系及電子研究所
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    Department of Electronics Engineering and Institute of Electronics
    We investigated annealing effects on the bipolar resistive switching characteristics and mechanism of the thin FeOx transition layer in a Ti/TiN/SiO2/FeOx/FePt structure by depositing a plasma-enhanced tetraethyl orthosilicate oxide onto the Fe-contented electrode. The electrical results show that the values of operation voltage, variation of electrical parameters and retention properties could be improved with the increasing thermal treatment budget. Tunneling electron microscope, X-ray diffraction, Auger electron spectroscopy and X-ray photon-emission spectra depth profiles were examined for cross-section image, crystallinity and composition analyses of the transition layer. In order to investigate the resistive switching mechanism and characterizations in Ti/TiN/SiO2/FeOx/FePt structure, the electrical parameters were extracted during set and reset process. The retention property at room temperature and 85 C was improved after the thermal treatment and maintains both resistance states over 6 x 10(4) s implies promising potential for future memory application. (C) 2011 Elsevier B.V. All rights reserved.
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    A Novel Varying-Bias Read Scheme for MLC and Wide Temperature Range TMO ReRAM
    (2016-11)
    Lin, Yu-Hsuan
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    Lee, Ming-Hsiu
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    Wu, Jau-Yi
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    Lin, Yu-Yu
    ;
    Lee, Feng-Ming
    Resistance of transition metal oxide (TMO) resistive random access memory (ReRAM) depends sharply on temperature, resulting in drastic memory window loss at high temperature. Thus, it is difficult to design the ReRAM that can serve a wide range of operating conditions. It is especially challenging to achieve multi-level-cell (MLC) ReRAM because of the large temperature dependency. This letter investigates both the temperature and read bias dependencies of WOx ReRAM, and found both can be well understood by a modified space-charge limited conduction model. Using this model, we have designed a novel read scheme that varies the read bias according to the device temperature and compensates for the temperature effect on cell resistance. Since TMO ReRAM devices depend on defect states, cell-to-cell and cycle-to-cycle variations are naturally large. An algorithm is designed to address the variability. A 1-Mb WOx ReRAM array is fabricated to both characterize the bias and temperature dependencies and verify the new read scheme. A large and constant memory window is preserved for MLC across a wide temperature range (-40 degrees C-125 degrees C), suitable for high-reliability applications.
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    高速操作及高資料保存特性SONOS型式快閃記憶體之研究
    (2008)
    莊紹勳
    ;
    Chung Steve S
    ;
    國立交通大學電子工程學系及電子研究所
    傳統的浮動閘極(floating gate) 快閃式記憶體，受限於資料保存(data retention)問 題，穿隧氧化層(tunnel oxide)無法繼續微縮，SONOS 則具有可微縮性(scalability)、可以 有較佳的資料保存、低電壓操作、適合箝入式(embedded)設計等優點。SONOS 結構快 閃式記憶體的研究，在國內研究則相當缺乏，本計劃著眼於此，規劃三年時程的研究計 劃，建立一套完整的SONOS Flash cell 架構，嘗試利用Nitride 介電層及金屬化合物電荷 儲存層(charge storage)結構的SONOS-type 快閃式記憶體，以達到同時可以高速操作及較 佳資料保存(dada retention)特性等優點，建立相關製程模組，並探討其漏電流機制及可 靠性的分析方法。 本計劃預期完成的工作有： 第一年計劃工作的執行，我們將更改傳統 SONOS 中ONO layer 的設計，將ONO layer 改為Nitride 介電層/金屬化合物/Nitride(NMN)結構，以期達到可以高速操作、具高可靠 性、較佳data retention 的SONOS 快閃式記憶體元件設計。主要工作包含：建立high-k nitride 做為tunnel oxide、成長高可靠性低漏電流tunnel oxide 技術、開發metal-storage node 材料，建立相關製程模組，以及各種不同tunnel nitride 結構、storage node 的各項 性能(performance)及可靠性的研究。 第二年主要是延續第一年的元件製作及各種操作模式，完成具體的可靠性評估，包含： Cell Endurance、Data retention 等的可靠性量測，元件在P/E cycling 以後，tunnel oxide 所造成氧化層傷害的可靠性量測方法研究及各項leakage current 模型建立，依第一年完 成的不同的tunnel nitride、blocking nitride 厚度條件sample，研究出scaling 的設計準則。 最後一年則是利用 metal-NC 技術取代前一年的電荷儲存層於SONOS cell 的製作，期能 達到更好的data retention 的目標及操作速度、operation window、可靠性等的評估，建立 一套利用metal-NC 技術於SONOS cell 製程與元件的設計準則。 最後成果預期可以有世界級水準的論文發表，研究成果更可做為產業界下一世代快閃記 憶體的重要參考。
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    非揮發性氧化鋯電阻式記憶元件於結構、特性與製程整合之相依性
    (2010)
    曾俊元
    ;
    TSENG TSEUNG-YUEN
    ;
    國立交通大學電子工程學系及電子研究所
    隨著近代消費性電子產品，如：手機、個人電腦、MP3 和數位相機等，需求愈增的腳步，非揮發 性記憶體已成為現今半導體工業之研發重點。電阻式非揮發性記憶體為“金屬/電阻層/金屬”的結構，具 有非破壞性讀取、多重記憶狀態、結構簡單及所需面積小等優點；然而，就目前電阻式非揮發性記憶 體的研究與實際應用上，寫入/抹除切換速度、操作電壓、記憶保持時間和可靠度性能等方面，仍有極 大的改善空間。 以氧化物作為電阻式記憶體的電阻轉態層之機制說法眾說紛紜，但根據已發表的文獻，以電場引 發微小缺陷區域且串聯成導電路徑(通稱“燈絲filament”)較為廣泛接受。但由於所謂燈絲的形成或斷裂 乃屬機率性，故電子藉燈絲為路徑所造成的導電性不易有效精準的調控。過去我們實驗室對於氧化鋯 (ZrO2)薄膜電阻式記憶體之研究成果顯示可成功地利用活性金屬鈦電極有效地侷限住ZrO2 薄膜中燈絲 的形成或斷裂的位置，不僅大幅地改善了ZrO2 薄膜中電阻態的轉換特性，且達到高可靠度的操作次 數，相關的研究成果已被報導；然而，為了進一步提升ZrO2 電阻式記憶體之效能，本計畫的構想是以 ZrO2 薄膜作為電阻層，經由薄膜內摻雜金屬、嵌入奈米晶粒、亦或電漿及奈米壓痕等表面處理，希望 可藉由外加異質缺陷方式有效地控制電阻層中之主要缺陷形成，更清楚地侷限並掌握燈絲導電路徑的 形成與斷裂之位置，進而降低操作電壓，與提升速度、可靠度等相關性能。 本計畫預定將以三年進行，第一年主要工作為利用摻雜金屬離子與嵌入金屬奈米晶粒於ZrO2 氧化 物薄膜，配合改變ZrO2 薄膜整體厚度以及熱處理條件，欲探討不同濃度的金屬摻雜以及不同種類金屬 奈米晶粒，對於電子捕捉能力的影響；並研究內含金屬摻雜以及金屬奈米晶粒之ZrO2 氧化物薄膜的電 流傳導機制，藉以瞭解記憶體切換機制與材料特性的相依性。第二年計畫以ZrO2 電阻層為主的記憶薄 膜，探討其表面經由電漿(plasma)與奈米壓痕(nano-indentation)等處理對元件記憶效應的影響，並觀察 其金屬電極與ZrO2 薄膜間的界面反應之於記憶效應的影響，期盼能藉此侷限並控制氧化鋯電阻式記憶 體的電阻轉態區域於一維度與二維度空間，進而改善電阻式記憶體之整體電性、可靠度等相關性能表 現。第三年的研究中，將實現電阻式記憶體於不同電路結構中，如整合一個非揮發性電阻式記憶元件 至標準互補式金氧半電晶體製程(CMOS process)中，並搭配一個存取電晶體或二極體作為一組記憶包 (memory cell)，亦或以記憶陣列(memory array)以實現電路結構。
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    具奈米點之電阻式記憶體元件製作與物理機制研究
    (2010)
    施敏
    ;
    SZE SIMON MIN
    ;
    國立交通大學電子工程學系及電子研究所
    隨著浮停閘非揮發性記憶體的尺寸持續微縮之下，浮停閘記憶體的穿遂氧化層面臨到元件可靠度 的問題。最主要是薄穿遂氧化層在多次的寫入與抹除之後，穿遂氧化層會產生漏電路徑，導致元件內 儲存的電荷消失，使得記憶狀態發生錯誤。近年來，電阻式切換記憶體被學界與業界廣泛的研究，以 期應用於非揮發性記憶體。有別於傳統的浮停閘元件，電阻式記憶體的結構主要由上電極/電阻轉態層 /下電極所構成，可利用電壓或者電流來改變轉態層內的阻值，且在電源移除後，仍然保留原來的電阻 值，而達到非揮發性記憶體的功能。由於電阻式記憶體並沒有傳統元件穿遂氧化層微縮的問題，且電 阻式記憶體具有操作電壓低、體積小與操作速度快等優點，被視為下世代非揮發性記憶體元件的主要 選擇。 本計畫將研究奈米點嵌入電阻式切換記憶體特性的影響，並探討記憶體的電阻轉態機制，藉由對 機制的釐清，改善電阻式記憶體的記憶特性。計畫的第一年，我們將發展具有奈米點之電阻式記憶 體的元件製程，並研究不同奈米點結構之電阻式記憶體，探討不同奈米點位置對於電阻轉換特性 的影響，並且也將研究單層與多層奈米點的差別，分析多層奈米點是否能進一步改善電阻轉換特 性的均勻度。第二年，我們將針對第一年所製作的奈米點嵌入式記憶體做完整的電性分析與物理 機制探討。目前電阻式記憶體的物理機制與操作特性，尚未有明確的結果，這些原因都將影響電 阻式記憶體的發展。在第二年中，我們將針對第一年所製作的記憶體元件，進行完整的電性量測， 包含操作參數的萃取與記憶體特性的探討，並結合元件的計算與模擬進而推論電阻式記憶體轉態 的完整物理機制，以及奈米點對電阻式記憶體造成影響的物理機制。為了更進一步釐清與驗證所 提的機制，我們將研究電阻式記憶體在變溫條件下之電阻轉換特性，並且利用低溫(300K~4K)量測環 境，排除因熱擾動所造成之效應，藉此研究其電阻轉換機制與溫度之關係，釐清元件的電流傳導機制， 再比對我們提出的模型，如此細節的探討將有助於電阻式記憶體的電阻轉換物理機制釐清，並建立正 確之物理機制模型。