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Stress-Induced Effects in Resting EEG Spectra Predict the Performance of SSVEP-Based BCI
(2020-08-01)
Zhang, Hao-Yan
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Stevenson, Cory E.
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Jung, Tzyy-Ping
;
Ko, Li-Wei
;
交大名義發表
Most research in Brain-Computer-Interfaces (BCI) focuses on technologies to improve accuracy and speed. Little has been done on the effects of subject variability, both across individuals and within the same individual, on BCI performance. For example, stress, arousal, motivation, and fatigue can all affect the electroencephalogram (EEG) signals used by a BCI, which in turn impacts performance. Overcoming the impact of such user variability on BCI performance is an impending and inevitable challenge for routine applications of BCIs in the real world. To systematically explore the factors affecting BCI performance, this study embeds a Steady-State Visually Evoked Potential (SSVEP) based BCI into a "game with a purpose" (GWAP) to obtain data over significant lengths of time, under both high- and low-stress conditions. Ten healthy volunteers played a GWAP that resembles popular match-three games, such as Jewel Quest, Zoo Boom, or Candy Crush. We recorded the target search time, target search accuracy, and EEG signals during gameplay to investigate the impacts of stress on EEG signals and BCI performance. We used Canonical Correlation Analysis (CCA) to determine whether the subject had found and attended to the correct target. The experimental results show that SSVEP target-classification accuracy is reduced by stress. We also found a negative correlation between EEG spectra and the SNR of EEG in the frontal and occipital regions during gameplay, with a larger negative correlation for the high-stress conditions. Furthermore, CCA also showed that when the EEG alpha and theta power increased, the search accuracy decreased, and the spectral amplitude drop was more evident under the high-stress situation. These results provide new, valuable insights into research on how to improve the robustness of BCIs in real-world applications.
A 2.36 mu W/Ch CMOS 8-Channel EEG Acquisition Unit with Input Protection Circuits for Applications Under Transcranial Direct Current Stimulation
(2019-01-01)
Wu, Chung-Yu
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Huang, Chi-Wei
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Tsai, Tzung-Lin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 0.18um-CMOS 8-channel EEG acquisition unit with input protection circuits is designed and fabricated for EEG monitoring under the transcranial direct current stimulation (tDCS). The capacitively-coupled chopper instrumentation amplifier (CCCIA) with chopper modulation is used to suppress flicker noise and amplify input EEG signals. To filter out high frequency noise with high linearity, the switched-capacitor low-pass filter (SC-LPF) is proposed. The switchedcapacitor amplifier (SC-Amp) is also proposed to drive ADC capacitor array. The input protection circuit (IPC) is implemented by I/O device to keep internal circuits from overstress and artifacts from the tDCS. A 10-bit SAR ADC with offset-calibration comparator is integrated for accurate ADC conversion. The fabricated EEG acquisition unit has programmable gain 57.5/67.6/78.5dB. The measured power dissipation of a single CCCIA circuit is 2.36 mu W per channel. The measured recovery time is 7.5ms after the tDCS stimulation. It has been verified that the designed chip can record real EEG signals.
An 1.97 mu W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring
(2018-01-01)
Chen, Pin-Wen
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Huang, Chi-Wei
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Wu, Chung-Yu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a 65nm-CMOS 8-channel Analog Front-End (AFE) acquisition circuit is designed and fabricated for long term EEG monitoring. The Capacitively-Coupled Chopper Instrumentation Amplifier (CCCIA) with chopper modulation is used to amplify input EEG signals and suppress flicker noise. To realize low high-pass corner and large Electrode DC Offset (EDO) rejection ability, a fast-settling Hybrid DC Servo Loop (HDSL) is proposed here. It contains Digital DSL (DDSL) and Analog DSL (ADSL) to achieve better trade-off among power consumption, area, and hardware complexity. An energy-efficient 10-bit SAR ADC with offset-calibration comparator is integrated for accurate A/D conversion. The chip is fabricated in 65nm CMOS technology. The measured overall power dissipation of the acquisition circuit is 1.97 mu W per channel. The input-referred noise of AFE Amplifier (AFEA) is 0.7 mu V in pass band, and the Noise Efficient Factor (NEF) of the CCCIA is 1.99. The measured HDSL calibration time is 125ms. The fabricated SAR ADC has the power consumption of 0.85 mu W under 1V supply and the SNDR of 59.8dB at 100kS/s with the Nyquist input frequency. This chip can record EEG signals successfully and the recorded signal has been verified by NeruScan SynAmps RT 64-channel amplifiers.
Inherent Fuzzy Entropy for the Improvement of EEG Complexity Evaluation
(2018-04-01)
Cao, Zehong
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Lin, Chin-Teng
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電機工程學系
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腦科學研究中心
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Department of Electrical and Computer Engineering
In recent years, the concept of entropy has been widely used to measure the dynamic complexity of signals. Since the state of complexity of human beings is significantly affected by their health state, developing accurate complexity evaluation algorithms is a crucial and urgent area of study. This paper proposes using inherent fuzzy entropy (Inherent FuzzyEn) and its multiscale version, which employs empirical mode decomposition and fuzzy membership function (exponential function) to address the dynamic complexity in electroencephalogram (EEG) data. In the literature, the reliability of entropy-based complexity evaluations has been limited by superimposed trends in signals and a lack of multiple time scales. Our proposed method represents the first attempt to use the Inherent FuzzyEn algorithm to increase the reliability of complexity evaluation in realistic EEG applications. We recorded the EEG signals of several subjects under resting condition, and the EEG complexity was evaluated using approximate entropy, sample entropy, FuzzyEn, and Inherent FuzzyEn, respectively. The results indicate that Inherent FuzzyEn is superior to other competing models regardless of the use of fuzzy or nonfuzzy structures, and has the most stable complexity and smallest root mean square deviation.
Spatial Filtering for EEG-Based Regression Problems in Brain-Computer Interface (BCI)
(2018-04-01)
Wu, Dongrui
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King, Jung-Tai
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Chuang, Chun-Hsiang
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Lin, Chin-Teng
;
Jung, Tzyy-Ping
Electroencephalogram (EEG) signals are frequently used in brain-computer interfaces (BCIs), but they are easily contaminated by artifacts and noise, so preprocessing must be done before they are fed into a machine learning algorithm for classification or regression. Spatial filters have been widely used to increase the signal-to-noise ratio of EEG for BCI classification problems, but their applications in BCI regression problems have been very limited. This paper proposes two common spatial pattern (CSP) filters for EEG-based regression problems in BCI, which are extended from the CSP filter for classification, by using fuzzy sets. Experimental results on EEG-based response speed estimation from a large-scale study, which collected 143 sessions of sustained-attention psychomotor vigilance task data from 17 subjects during a 5-month period, demonstrate that the two proposed spatial filters can significantly increase the EEG signal quality. When used in LASSO and k-nearest neighbors regression for user response speed estimation, the spatial filters can reduce the root-mean-square estimation error by 10.02-19.77%, and at the same time increase the correlation to the true response speed by 19.39-86.47%.
An 8-Channel Chopper-Stabilized Analog Front-End Amplifier for EEG Acquisition in 65-nm CMOS
(2015)
Wu, Chung-Yu
;
Ho, Chia-Shiung
;
電子工程學系及電子研究所
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生醫電子轉譯研究中心
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Department of Electronics Engineering and Institute of Electronics
An 8-channel chopper-stabilized analog front-end amplifier (AFEA) is designed in 65-nm CMOS for continuous EEG signal acquisition. The AFEA is composed of eight capacitively coupled chopper instrumentation amplifiers (CCCIAs) with chopper-stabilized circuits and band-pass filters, a multiplexed transconductor, and a transimpedance amplifier. The CCCIA employs an inverter-based folded-cascode amplifier (IBFC) to achieve a better noise-to-power tradeoff and a high gain under 1 V power supply, a DC servo loop to suppress electrode offset and provide a low high-pass corner, a low power ripple reduction loop to suppress chopping ripple, and a positive feedback loop to boost its input impedance. The fabricated AFEA has 59.1/69.8/78 dB programmable gain and 0.81 mu Vrms input-referred noise in a bandwidth of 0.5-100 Hz. The measured power consumption of a single CCCIA is 0.87 mu W. The proposed CCCIA has a lower NEF of 2.97 than other CCCIA for EEG acquisition.
Neural Correlates of Mathematical Problem Solving
(2015-03-01)
Lin, Chun-Ling
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Jung, Melody
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Wu, Ying Choon
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She, Hsiao-Ching
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Jung, Tzyy-Ping
This study explores electroencephalography (EEG) brain dynamics associated with mathematical problem solving. EEG and solution latencies (SLs) were recorded as 11 neurologically healthy volunteers worked on intellectually challenging math puzzles that involved combining four single-digit numbers through basic arithmetic operators (addition, subtraction, division, multiplication) to create an arithmetic expression equaling 24. Estimates of EEG spectral power were computed in three frequency bands - theta (4-7Hz), alpha (8-13Hz) and beta (14-30 Hz) - over a widely distributed montage of scalp electrode sites. The magnitude of power estimates was found to change in a linear fashion with SLs - that is, relative to a base of power spectrum, theta power increased with longer SLs, while alpha and beta power tended to decrease. Further, the topographic distribution of spectral fluctuations was characterized by more pronounced asymmetries along the left-right and anterior-posterior axes for solutions that involved a longer search phase. These findings reveal for the first time the topography and dynamics of EEG spectral activities important for sustained solution search during arithmetical problem solving.

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