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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Now showing 1 - 7 of 7
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    Energy Transformation Between the Inductor and the Power Transistor for the Unclamped Inductive Switching (UIS) Test
    (2020-06-01)
    Nidhi, Karuna
    ;
    Lee, Jian-Hsing
    ;
    Huang, Shao-Chang
    ;
    Ker, Ming-Dou
    ;
    交大名義發表
    The fundamental model of energy transformation between the inductor and the power transistor for the unclamped inductive switching (UIS) test is inspected. Based on the experimental results, the energy stored in the inductor at the period of the channel turn-on can be dissipated by the power transistor after the channel is turned off. In this work, a new theoretical model to well describe the electrical and thermal behaviors of the power transistor during the unclamped inductive switching (UIS) test has been identified and analyzed with the experimental silicon results under different inductor values in 0.15 mu m BCD process. The total UIS energy reduced due to series resistance of the inductor and the power transistor has been theoretically explained and well matches with the experimental measured results on silicon.
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    A Robust Fully-Integrated Digital-Output Inductive CMOS-MEMS Accelerometer with Improved Inductor Quality Factor
    (2019-11-01)
    Chiu, Yi
    ;
    Liu, Hsuan-Wu
    ;
    Hong, Hao-Chiao
    ;
    電機工程學系
    ;
    Department of Electrical and Computer Engineering
    This paper presents the design, fabrication, and characterization of an inductive complementary metal oxide semiconductor micro-electromechanical systems (CMOS-MEMS) accelerometer with on-chip digital output based on LC oscillators. While most MEMS accelerometers employ capacitive detection schemes, the proposed inductive detection scheme is less susceptible to the stress-induced structural curling and deformation that are commonly seen in CMOS-MEMS devices. Oscillator-based frequency readout does not need analog to digital conversion and thus can simplify the overall system design. In this paper, a high-Q CMOS inductor was connected in series with the low-Q MEMS sensing inductor to improve its quality factor. Measurement results showed the proposed device had an offset frequency of 85.5 MHz, sensitivity of 41.6 kHz/g, noise floor of 8.2 mg/root Hz, bias instability of 0.94 kHz (11 ppm) at an average time of 2.16 s, and nonlinearity of 1.5% full-scale.
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    Analytical Noise Optimization of Single-/Dual-Band MOS LNAs With Substrate and Metal Loss Effects of Inductors
    (2019-07-01)
    Chang, Wei Ling
    ;
    Meng, Chinchun
    ;
    Ni, Jung-Hung
    ;
    Ch, Kai-Chun
    ;
    Chang, Chih-Kai
    Analytical noise formulations and design optimization of single- and dual-band inductively source-degenerated MOS low-noise amplifiers (LNAs) with the substrate and metal loss effects of on-chip inductors are established in this paper. It reveals that the noise figures of both single-/dual-band LNAs degrade substantially under the consideration of the loss effects. However, by increasing the device size, the noise optimization methodology of simultaneous noise and input match for a single-band LNA still holds true with concern for the loss effects. For a dual-band LNA, analytical noise optimization for a balanced noise design is established for inductors with metal and substrate loss and indicates a larger device size. The substrate and metal loss effects of inductors can be mitigated using integrated passive device (IPD) process for the input match network. The demonstrated single-band 0.18-mu m MOS LNAs with and without IPD process show noise figures of 1.53 and 2.52 dB at 2.4 GHz, respectively. Subsequently, the implemented dual-band 0.18-mu m MOS LNAs with and without IPD process show noise figures of 1.6/2.6 and 3.25/4.1 dB at 2.4/5 GHz, respectively.
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    A Combined Process of Liftoff and Printing for the Fabrication of Scalable Inkjet Printed Microstructures on a Flexible Substrate
    (2015-04-01)
    Fu, Yu-Min
    ;
    Liang, Yen R.
    ;
    Cheng, Yu-Ting
    ;
    Wu, Pu-Wei
    ;
    材料科學與工程學系
    In this paper, a combined process of liftoff and printing (CPLoP) techniques is introduced to realize size-scalable printed silver microstructures with line widths ranging from 5 to 70 mu m and resistivities of similar to 9.8 mu Omega . cm on a flexible polyimide substrate via thermal sintering at 300 degrees C for 30 min. In addition, a printed interdigitated capacitor with an electrode line width and spacing of 10 mu m and a printed spiral square inductor with a 10-mu m line width and 5-mu m spacing in an area of 1 mm(2) have been successfully demonstrated with an area capacitance and inductance of 0.43 pF/mm(2) at 10 KHz and 1.054 mu H/mm(2) up to 100 KHz, respectively, which are the orders of magnitude performance improvement in comparison with the contemporary inkjet-printed capacitors and inductors. Owing to the significant reduction of energy demand in processing tools and waste generation in processing materials, the results have revealed that the CPLoP process can facilitate the advancement of printing manufacture technology for microelectronics applications.
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    A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities
    (2006)
    Guo, J. C.
    ;
    Tan, T. Y.
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A broadband and scalable model is developed to accurately simulate on-chip inductors of various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies up to 20 GHz, even beyond resonance. A new scheme of RLC networks is deployed for spiral coils and substrate to account for 3D eddy current, substrate return path, and spiral coil to substrate coupling effects, etc. The 3D eddy current is identified as the key element essential to accurately simulate broadband characteristics. EM simulation using ADS momentum is conducted to predict the on-chip inductor performance corresponding to wide range of substrate resistivities (rho(Si)=0.05 similar to 1K Omega-cm). Three operation modes such as TEM, slow-wave, and eddy current are reproduced. The model parameters manifest themselves physics-base through relevant correlation with rho(Si) over three operation modes. The onset of slow-wave mode can be consistently explained by a key element (R-P) introduced in our model, which accounts for the conductor loss due to eddy current arising from magnetic field coupling through substrate return path. This broadband and scalable model is useful for RF circuit simulation. Besides, it can facilitate optimization design of on-chip inductors through physics-based model parameters relevant to varying substrate resistivities.
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    Item type:Item,
    A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities
    (2006-01-01)
    Guo, J. C.
    ;
    Tan, T. Y.
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A broadband and scalable model is developed to accurately simulate on-chip inductors of various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies up to 20 GHz, even beyond resonance. A new scheme of RLC networks is deployed for spiral coils and substrate to account for 3D eddy current, substrate return path, and spiral coil to substrate coupling effects, etc. The 3D eddy current is identified as the key element essential to accurately simulate broadband characteristics. EAI simulation using ADS momentum is conducted to predict the on-chip inductor performance corresponding to wide range of substrate resistivities (rho(Si)=0.05 similar to 1K Omega-cm). Three operation modes such as TEM, slow-wave, and eddy current are reproduced. The model parameters manifest themselves physics-base through relevant correlation with psi over three operation modes. The onset of slow-wave mode can be consistently explained by a key element (R-p) introduced in our model, which accounts for the conductor loss due to eddy current arising from magnetic field coupling through substrate return path. This broadband and scalable model is useful for RF circuit simulation. Besides, it can facilitate optimization design of on-chip inductors through physics-based model parameters relevant to varying substrate resistivities.
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    Broadband and scalable on-silicon-chip inductor model for varying substrate resistivities
    (2006)
    Guo, J. C.
    ;
    Tan, T. Y.
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A broadband and scalable model is developed to accurately simulate on-chip inductors of various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies up to 20 GHz, even beyond resonance. A new scheme of RLC networks is deployed for spiral coils and substrate to account for 3D eddy current, substrate return path, and spiral coil to substrate coupling effects, etc. The 3D eddy current is identified as the key element essential to accurately simulate broadband characteristics. A key element (R(P)) introduced in our model can successfully accounts for the conductor loss due to eddy current arising from magnetic field coupling through substrate return path. This broadband and scalable model is useful for RF circuit simulation. Besides, it can facilitate on-chip inductor design and optimization through physics-based model parameters relevant to lossy substrate.